NSC800 Datasheet, PDF (29/76 Pages) National Semiconductor (TI) – NSC800TM High-Performance Low-Power CMOS Microprocessor

12 1 Instruction Set Index (Continued)
Alphabetical
Assembly
Mnemonic
Operation
DI
DJNZ d
Disable interrupts
Decrement B and jump relative B ⁱ 0
EI
EX (SP) ss
EX AF A’F’
EX DE HL
EXX
Enable interrupts
Exchange the location (SP) with register ss
Exchange the contents of AF and A’F’
Exchange the contents of DE and HL
Exchange the contents of BC DE and HL with the contents
of B’C D’E’ and H’L’ respectively
HALT
Halt (wait for interrupt or reset)
IM 0
IM 1
IM 2
IN A (n)
IN r (C)
INC m₁
INC r
INC rr
IND
INDR
INI
INIR
Set interrupt mode 0
Set interrupt mode 1
Set interrupt mode 2
Load Accumulator with input from device (n)
Load register r with input from device (C)
Increment data in memory location m₁
Increment register r
Increment contents of register pair rr
Load location (HL) with input from port (C) decrement HL and B
Load location (HL) with input from port (C) decrement HL and B repeat until B e 0
Load location (HL) with input from port (C) increment HL decrement B
Load location (HL) with input from port (C) increment HL decrement B
repeat until B e 0
JP cc nn
JP nn
JP (ss)
JR d
JR kk d
Jump to location nn if condition cc is true
Unconditional jump to location nn
Unconditional jump to location (ss)
Unconditional jump relative to PC a d
Jump relative to PC a d if kk true
LD A I
LD A m₂
LD A R
LD I A
LD m₁ n
LD m₁ r
LD m₂ A
LD (nn) rr
LD r m₁
LD r n
LD R A
LD r_d r_s
LD rr (nn)
LD rr nn
LD SP ss
LDD
LDDR
LDI
LDIR
Load Accumulator with register I contents
Load Accumulator from location m₂
Load Accumulator with register R contents
Load register I with Accumulator contents
Load memory with immediate data n
Load memory from register r
Load memory from Accumulator
Load memory location nn with register pair rr
Load register r from memory
Load register with immediate data n
Load register R from Accumulator
Load destination register r_d from source register r_s
Load register pair rr from memory location nn
Load register pair rr with immediate data nn
Load SP from register pair ss
Load location (DE) with location (HL) decrement DE HL and BC
Load location (DE) with location (HL) decrement DE HL and BC repeat until BC e 0
Load location (DE) with location (HL) increment DE and HL decrement BC
Load location (DE) with location (HL) increment DE and HL decrement BC
repeat until BC e 0
NEG
NOP
Negate Accumulator (2’s complement)
No operation
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