NSC800 Datasheet, PDF (34/76 Pages) National Semiconductor (TI) – NSC800TM High-Performance Low-Power CMOS Microprocessor

12 5 16-Bit Loads
REGISTER TO REGISTER
LD rr nn
Load 16-bit register pair with immediate data
rr w nn
No flags affected
7 6 5 4 3 2 1 0 LD BC nn
00
rp 0 0 0 1
LD DE nn
LD HL nn
n (low-order byte)
LD SP nn
n (high-order byte)
Timing
M cycles 3
T states 10 (4 3 3)
Addressing Mode
Source Immediate Extended
Destination Register
76 5 43210
1 1 N_X 1 1 1 0 1
LD IX nn (for N_X e 0)
LD IY nn (for N_X e 1)
00 1 00001
n (low-order byte)
n (high-order byte)
Timing
Addressing Mode
M cycles 4
T states 14 (4 4 3 3)
Source Immediate Extended
Destination Register
LD SP ss
Load the SP from 16-bit register ss
SP w ss
No flags affected
76543210
1 1 1 1 1 0 0 1 LD SP HL
Timing
M cycles 1
T states 6
Addressing Mode
Source Register
Destination Register (Implied)
76 5 43210
1 1 N_X 1 1 1 0 1
LD SP IX (for N_X e 0)
LD SP IY (for N_X e 1)
11 1 11001
Timing
Addressing Mode
M cycles 2
T states 10 (4 6)
Source Register
Destination Register (Implied)
REGISTER TO MEMORY
LD (nn) rr
Load memory location nn with contents of 16-bit register rr
w (nn)
rr_L
No flags affected
w (nn a 1)
rr_H
76543210
LD (nn) HL
0 0 1 0 0 0 1 0 _{(note an alternate}
opcode below)
n (low-order byte)
n (high-order byte)
Timing
M cycles 5
T states 16 (4 3 3 3 3)
Addressing Mode
Source Register
Destination Direct
7 6 5 4 3 2 1 0 LD (nn) BC
11101101
LD (nn) DE
LD (nn) HL
0 1 rp 0 0 1 1 LD (nn) SP
n (low-order byte)
n (high-order byte)
Timing
M cycles 6
T states 20 (4 4 3 3 3 3)
Addressing Mode
Source Register
Destination Direct
76 5 43210
1 1 N_X 1 1 1 0 1
LD (nn) IX (for N_X e 0)
LD (nn) IY (for N_X e 1)
00 1 00010
n (low-order byte)
n (high-order byte)
Timing
Addressing Mode
M cycles 6
T states 20 (4 4 3 3 3 3)
Source Register
Destination Direct
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