NSC800 Datasheet, PDF (5/76 Pages) National Semiconductor (TI) – NSC800TM High-Performance Low-Power CMOS Microprocessor

4 0 AC Electrical Characteristics V_CC e 5V g10% GND e 0V unless otherwise specified (Continued)
Symbol
Parameter
NSC800-1 NSC800-3 NSC800-35 NSC800-4 _Units
Min Max Min Max Min Max Min Max
Notes
T_H(ADH)1 A(8 – 15) Hold Time During 0
0
0
Opcode Fetch
0
ns
T_H(ADH)2 A(8 – 15) Hold Time During 400
100
85
Memory or IO RD and WR
60
ns
T_H(ADL) AD(0 – 7) Hold Time
100
60
35
T_H(WD) Write Data Hold Time
400
100
85
t_INH
Interrupt Hold Time
0
0
0
t_INS
Interrupt Set-Up Time
100
50
50
t_NMI
Width of NMI Input
50
30
25
t_RDH
Data Hold after Read
0
0
0
t_RFLF
RFSH Rising to ALE
60
50
45
Falling
30
ns
75
ns
0
ns
45
ns
20
ns
0
ns
40
ns
t_RL(MR) RD Rising to ALE Rising 390
100
50
(Memory Read)
45
ns
t_S(AD)
AD(0–7) Set-Up Time
300
45
45
t_S(ALE) A(8 – 15) SO SI IO M
350
70
55
Set-Up Time
40
ns
50
ns
t_S(WD) Write Data Set-Up Time
385
75
35
30
ns
t_W(ALE) ALE Width
430
130
115
100
ns
t_WH
WAIT Hold Time
0
0
0
0
ns
t_W(I)
Width of INTR RSTA-C 500
200
140
125
ns
PS BREQ
t_W(INTA) INTA Strobe Width
1000
400
225
200
ns Add two t states for first
INTA of each interrupt
response string Add t for
each WAIT state
t_WL
WR Rising to ALE Rising 450
130
70
70
ns
t_W(RD) Read Strobe Width During 960
360
210
185
ns Add t for each WAIT
Opcode Fetch
State Add t 2 for Memory
Read Cycles
t_W(RFSH) Refresh Strobe Width
1925
725
450
395
ns
t_WS
WAIT Set-Up Time
100
70
60
55
ns
t_W(WAIT) WAIT Input Width
550
250
195
175
ns
t_W(WR) Write Strobe Width
985
370
250
220
ns
t_XCF
XIN to Clock Falling
25 100 15 95 5 90 5 80 ns
t_XCR
XIN to Clock Rising
25 85 15 85 5 90 5 80 ns
Note 1 Test conditions t e 1000 ns for NSC800-1 400 ns for NSC800 285 ns for NSC800-35 250 ns for NSC800-4
Note 2 Output timings are measured with a purely capacitive load of 100 pF
Add t for each WAIT state
5