NSC800 Datasheet, PDF (44/76 Pages) National Semiconductor (TI) – NSC800TM High-Performance Low-Power CMOS Microprocessor

12 7 16-Bit Arithmetic (Continued)
DEC rr
Decrement the contents of the 16-bit register rr
rr w rr b 1
No flags affected
7 6 5 4 3 2 1 0 DEC BC
0 0 rp 1 0 1 1 ^{DEC DE}
DEC HL
DEC SP
Timing
M cycles 1
T states 6
Addressing Mode
Register
76 5 43210
1 1 N_X 1 1 1 0 1
DEC IX (for N_Xe0)
DEC IY (for N_Xe1)
00 1 01011
Timing
Addressing Mode
M cycles
T states
Register
2
10 (4 6)
12 8 Bit Set Reset and Test
REGISTER
SET b r
Bit b in register r is set
R_b w 1
7654321
No flags affected
0
11001011
11
b
r
Timing
Addressing Mode
M cycles 2
T states 8 (4 4)
Bit Register
RES b r
Bit b in register r is reset
r_b w 0
7654321
No flags affected
0
11001011
10
b
r
Timing
Addressing Mode
M cycles 2
T states 8 (4 4)
Bit Register
BIT b r
Bit b in register r is tested with the result put in the Z flag
Z w r_b
S Undefined
Z Inverse of tested bit
H Set
P V Undefined
N Reset
CNA
76543210
11001011
01
b
r
Timing
Addressing Mode
M cycles 2
T states 8 (4 4)
Bit Register
MEMORY
SET b m₁
Bit b in memory location m₁ is set
w m_1b
1
No flags affected
76543210
1 1 0 0 1 0 1 1 SET b (HL)
11
b
110
Timing
M cycles 4
T states 15 (4 4 4 3)
Addressing Mode
Bit Register Indirect
76 5 43210
1 1 N_X 1 1 1 0 1
SET b (IXad) (for N_Xe0)
SET b (IYad) (for N_Xe1)
11 0 01011
d
11
b 110
Timing
Addressing Mode
M cycles 6
T states 23 (4 4 3 5 4 3)
Bit Indexed
RES b m₁
Bit b in memory location m₁ is reset
w m_1b
0
No flags affected
76543210
1 1 0 0 1 0 1 1 RES b (HL)
10
b
110
Timing
M cycles 4
T states 15 (4 4 4 3)
Addressing Mode
Bit Register Indirect
76 5 43210
1 1 N_X 1 1 1 0 1
RES b (IXad) (for N_Xe0)
RES b (IYad) (for N_Xe1)
11 0 01011
d
10
b 110
Timing
Addressing Mode
M cycles 6
T states 23 (4 4 3 5 4 3)
Bit Indexed
44