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NSC800 Datasheet, PDF (67/76 Pages) National Semiconductor (TI) – NSC800TM High-Performance Low-Power CMOS Microprocessor
12 16 Instruction Set Numerical Order (Continued)
Op Code Mnemonic
Op Code Mnemonic
CBB7
CBB8
CBB9
CBBA
CBBB
CBBC
CBBD
CBBE
CBBF
CBC0
CBC1
CBC2
CBC3
CBC4
CBC5
CBC6
CBC7
CBC8
CBC9
CBCA
CBCB
CBCC
CBCD
CBCE
CBCF
CBD0
CBD1
CBD2
CBD3
CBD4
CBD5
CBD6
CBD7
CBD8
CBD9
CBDA
CBDB
CBDC
CBDD
CBDE
CBDF
CBE0
CBE1
CBE2
CBE3
CBE4
CBE5
CBE6
CBE7
CBE8
CBE9
CBEA
CBEB
RES 6 A
RES 7 B
RES 7 C
RES 7 D
RES 7 E
RES 7 H
RES 7 L
RES 7 (HL)
RES 7 A
SET 0 B
SET 0 C
SET 0 D
SET 0 E
SET 0 H
SET 0 L
SET 0 (HL)
SET 0 A
SET 1 B
SET 1 C
SET 1 D
SET 1 E
SET 1 H
SET 1 L
SET 1 (HL)
SET 1 A
SET 2 B
SET 2 C
SET 2 D
SET 2 E
SET 2 H
SET 2 L
SET 2 (HL)
SET 2 A
SET 3 B
SET 3 C
SET 3 D
SET 3 E
SET 3 H
SET 3 L
SET 3 (HL)
SET 3 A
SET 4 B
SET 4 C
SET 4 D
SET 4 E
SET 4 H
SET 4 L
SET 4 (HL)
SET 4 A
SET 5 B
SET 5 C
SET 5 D
SET 5 E
(nn)eAddress of memory location
nneData (16 bit)
neData (8-bit)
dedisplacement
d2edb2
CBEC
CBED
CBEE
CBEF
CBF0
CBF1
CBF2
CBF3
CBF4
CBF5
CBF6
CBF7
CBF8
CBF9
CBFA
CBFB
CBFC
CBFD
CBFE
CBFF
CCnn
CDnn
CEn
CF
D0
D1
D2nn
D3n
D4nn
D5
D6n
D7
D8
D9
DAnn
DBn
DCnn
DD09
DD19
DD21nn
DD22nn
DD23
DD29
DD2Ann
DD2B
DD34d
DD35d
DD36dn
DD39
DD46d
DD4Ed
DD56d
DD5Ed
SET 5 H
SET 5 L
SET 5 (HL)
SET 5 A
SET 6 B
SET 6 C
SET 6 D
SET 6 E
SET 6 H
SET 6 L
SET 6 (HL)
SET 6 A
SET 7 B
SET 7 C
SET 7 D
SET 7 E
SET 7 H
SET 7 L
SET 7 (HL)
SET 7 A
CALL Z nn
CALL nn
ADC A n
RST 8
RET NC
POP DE
JP NC nn
OUT (n) A
CALL NC nn
PUSH DE
SUB n
RST 10H
RET C
EXX
JP C nn
IN A (n)
CALL C nn
ADD IX BC
ADD IX DE
LD IX nn
LD (nn) IX
INC IX
ADD IX IX
LD IX (nn)
DEC IX
INC (IXad)
DEC (IXad)
LD (IXad) n
ADD IX SP
LD B (IXad)
LD C (IXad)
LD D (IXad)
LD E (IXad)
67
Op Code
DD66d
DD6Ed
DD70d
DD71d
DD72d
DD73d
DD74d
DD75d
DD77d
DD7Ed
DD86d
DD8Ed
DD96d
DD9Ed
DDA6d
DDAEd
DDB6d
DDBEd
DDCBd06
DDCBd0E
DDCBd16
DDCBd1E
DDCBd26
DDCBd2E
DDCBd3E
DDCBd46
DDCBd4E
DDCBd56
DDCBd5E
DDCBd66
DDCBd6E
DDCBd76
DDCBd7E
DDCBd86
DDCBd8E
DDCBd96
DDCBd9E
DDCBdA6
DDCBdAE
DDCBdB6
DDCBdBE
DDCBdC6
DDCBdCE
DDCBdD6
DDCBdDE
DDCBdE6
DDCBdEE
DDCBdF6
DDCBdFE
DDE1
DDE3
DDE5
DDE9
Mnemonic
LD H (IXad)
LD L (IXad)
LD (IXad) B
LD (IXad) C
LD (IXad) D
LD (IXad) E
LD (IXad) H
LD (IXad) L
LD (IXad) A
LD A (IXad)
ADD A (IXad)
ADC A (IXad)
SUB (IXad)
SBC A (IXad)
AND (IXad)
XOR (IXad)
OR (IXad)
CP (IXad)
RLC (IXad)
RRC (IXad)
RL (IXad)
RR (IXad)
SLA (IXad)
SRA (IXad)
SRL (IXad)
BIT 0 (IXad)
BIT 1 (IXad)
BIT 2 (IXad)
BIT 3 (IXad)
BIT 4 (IXad)
BIT 5 (IXad)
BIT 6 (IXad)
BIT 7 (IXad)
RES 0 (IXad)
RES 1 (IXad)
RES 2 (IXad)
RES 3 (IXad)
RES 4 (IXad)
RES 5 (IXad)
RES 6 (IXad)
RES 7 (IXad)
SET 0 (IXad)
SET 1 (IXad)
SET 2 (IXad)
SET 3 (IXad)
SET 4 (IXad)
SET 5 (IXad)
SET 6 (IXad)
SET 7 (IXad)
POP IX
EX (SP) IX
PUSH IX
JP (IX)