NSC800 Datasheet, PDF (33/76 Pages) National Semiconductor (TI) – NSC800TM High-Performance Low-Power CMOS Microprocessor

12 4 8-Bit Loads (Continued)
LD m₂ A
Load memory from the Accumulator
m₂ w A
No flags affected
76543210
0 0 0 0 0 0 1 0 LD (BC) A
0 0 0 1 0 0 1 0 LD (DE) A
Timing
M cycles 2
T states 7 (4 3)
Addressing Mode
Source Register (Implied)
Destination Register Indirect
76543210
0 0 1 1 0 0 1 0 LD (nn) A
n (low-order byte)
n (high-order byte)
Timing
Addressing Mode
M cycles 4
T states 3 (4 3 3 3)
Source Register (Implied)
Destination Direct
LD m₁ n
Load memory with immediate data
m₁ w n
No flags affected
76543210
0 0 1 1 0 1 1 0 LD(HL) n
n
Timing
M cycles 3
T states 10 (4 3 3)
Addressing Mode
Source Immediate
Destination Register Indirect
76 5 43210
1 1 N_X 1 1 1 0 1
LD (IX a d) n(for N_X e 0)
LD (IY a d) n(for N_X e 1)
00 1 10110
d
n
Timing
Addressing Mode
M cycles 5
T states 19 (4 4 3 5 3)
Source Immediate
Destination Indexed
MEMORY TO REGISTER
LD r m₁
Load register r from memory location m₁
r w m₁
No flags affected
76543210
01
r
1 1 0 LD R (HL)
Timing
M cycles 2
T states 7 (4 3)
Addressing Mode
Source Register Indirect
Destination Register
76 5 43210
LD r (IX a d) (for N_Xe0)
1 1 N_X 1 1 1 0 1 _{LD r (IY a d) (for NXe1)}
01
r
110
d
Timing
Addressing Mode
M cycles 5
T states 19 (4 4 3 5 3)
Source Indexed
Destination Register
LD A m₂
Load the Accumulator from memory location m₂
A w m₂
No flags affected
76543210
LD A (BC)
00001010
0 0 0 1 1 0 1 0 LD A (DE)
Timing
M cycles 2
T states 7 (4 3)
Addressing Mode
Source Register Indirect
Destination Register (Implied)
76543210
0 0 1 1 1 0 1 0 LD A (nn)
n (low-order byte)
n (high-order byte)
Timing
Addressing Mode
M cycles 4
T states 13 (4 3 3 3)
Source Immediate Extended
Destination Register (Implied)
33