NSC800 Datasheet, PDF (46/76 Pages) National Semiconductor (TI) – NSC800TM High-Performance Low-Power CMOS Microprocessor

12 9 Rotate and Shift (Continued)
76543210
1 1 0 0 1 0 1 1 RRC r
00001
r
(Note alternate for
A register below)
Timing
M cycles
T states
Addressing Mode
Register
76543210
2
8 (4 4)
0 0 0 0 1 1 1 1 RRCA
Timing
M cycles 1
T states 4
Addressing Mode
Implied
(Note RRCA does not affect S Z or P V flags )
RR r
Rotate register r right through carry
TL C 5171–60
S Set if result is negative
Z Set if result is zero
H Reset
P V Set if result parity is even
N Reset
C Set according to bit 0 of r
76543210
1 1 0 0 1 0 0 1 RR r
00011
r
(Note alternate for
A register below)
Timing
M cycles
T states
Addressing Mode
Register
76543210
2
8 (4 4)
0 0 0 1 1 1 1 1 RRA
Timing
M cycles 1
T states 4
Addressing Mode
Implied
(Note RRA does not affect S Z or P V flags )
SLA r
Shift register r left arithmetric
TL C 5171–61
S Set if result is negative
Z Set if result is zero
H Reset
P V Set if result parity is even
N Reset
C Set according to bit 7 of r
76543210
11001011
00100
r
Timing
Addressing Mode
M cycles
T states
Register
2
8 (4 4)
SRA r
Shift register r right arithmetic
TL C 5171 – 62
S Set if result is negative
Z Set if result is zero
H Reset
P V Set if result parity is even
N Reset
C Set according to bit 0 of r
76543210
11001011
00101
r
Timing
Addressing Mode
M cycles
T states
Register
2
8 (4 4)
SRL r
Shift register r right logical
TL C 5171 – 63
S Reset
Z Set if result is zero
H Reset
P V Set if result parity is even
N Reset
C Set according to bit 0 of r
76543210
11001011
00111
Timing
Addressing Mode
r
M cycles
T states
Register
2
8 (4 4)
46