NSC800 Datasheet, PDF (22/76 Pages) National Semiconductor (TI) – NSC800TM High-Performance Low-Power CMOS Microprocessor

9 0 Timing and Control (Continued)
A reset to the CPU will force both IFF₁ and IFF₂ to the reset
state disabling maskable interrupts They can be enabled by
an EI instruction at any time by the programmer When an EI
instruction is executed any pending interrupt requests will
not be accepted until after the instruction following EI has
been executed This single instruction delay is necessary in
situations where the following instruction is a return instruc-
tion and interrupts must not be allowed until the return has
been completed The EI instruction sets both IFF₁ and IFF₂
to the enable state When the CPU accepts an interrupt
both IFF₁ and IFF₂ are automatically reset inhibiting further
interrupts until the programmer wishes to issue a new EI
instruction Note that for all the previous cases IFF₁ and
IFF₂ are always equal
The function of IFF₂ is to retain the status of IFF₁ when a
non-maskable interrupt occurs When a non-maskable inter-
rupt is accepted IFF₁ is reset to prevent further interrupts
until reenabled by the programmer Thus after a non-mask-
able interrupt has been accepted maskable interrupts are
disabled but the previous state of IFF₁ is saved by IFF₂
FIGURE 17 Interrupt Mode 2
TL C 5171 – 27
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