NSC800 Datasheet, PDF (21/76 Pages) National Semiconductor (TI) – NSC800TM High-Performance Low-Power CMOS Microprocessor

9 0 Timing and Control (Continued)
Note 1 This is the only machine cycle that does not have an RD WR or INTA strobe but will accept a wait strobe
FIGURE 16 Non-Maskable and Restart Interrupt Machine Cycle
TL C 5171 – 24
The NSC800 also provides one more general purpose inter-
rupt request input INTR When enabled the CPU responds
to INTR in one of the three modes defined by instruction
IM0 IM1 and IM2 for modes 0 1 and 2 respectively Fol-
lowing reset the CPU automatically enables mode 0
Interrupt (INTR) Mode 0 The CPU responds to an interrupt
request by providing an INTA (interrupt acknowledge)
strobe which can be used to gate an instruction from a
peripheral onto the data bus The CPU inserts two wait
states during the first INTA cycle to allow the interrupting
device (or its controller) ample time to gate the instruction
and determine external priorities (Figure 18 ) This can be
any instruction from one to four bytes The most popular
instruction is one-byte call (restart instruction) or a three-
byte call (CALL NN instruction) If it is a three-byte call the
CPU issues a total of three INTA strobes The last two
(which do not include wait states) read NN
Note If the instruction stored in the ICU doesn’t require the PC to be
pushed onto the stack (eq JP nn) then the PC will not be pushed
Interrupt (INTR) Mode 1 Similar to restart interrupts ex-
cept the restart location is X’0038 (Figure 18 )
Interrupt (INTR) Mode 2 With this mode the programmer
maintains a table that contains the 16-bit starting address of
every interrupt service routine This table can be located
anywhere in memory When the CPU accepts a Mode 2
interrupt (Figure 17 ) it forms a 16-bit pointer to obtain the
desired interrupt service routine starting address from the
table The upper 8 bits of this pointer are from the contents
of the I register The lower 8 bits of the pointer are supplied
by the interrupting device with the LSB forced to zero The
programmer must load the interrupt vector prior to the inter-
rupt occurring The CPU uses the pointer to get the two
adjacent bytes from the interrupt service routine starting ad-
dress table to complete 16-bit service routine starting ad-
dress The first byte of each entry in the table is the least
significant (low-order) portion of the address The program-
mer must obviously fill this table with the desired addresses
before any interrupts are to be accepted
Note that the programmer can change this table at any time
to allow peripherals to be serviced by different service rou-
tines Once the interrupting device supplies the lower por-
tion of the pointer the CPU automatically pushes the pro-
gram counter onto the stack obtains the starting address
from the table and does a jump to this address
The interrupts have fixed priorities built into the NSC800 as
NMI
0066
(Highest Priority)
RSTA
003C
RSTB
0034
RSTC
002C
INTR
0038
(Lowest Priority)
Interrupt Enable Interrupt Disable The NSC800 has two
types of interrupt inputs a non-maskable interrupt and four
software maskable interrupts The non-maskable interrupt
(NMI) cannot be disabled by the programmer and will be
accepted whenever a peripheral device requests an inter-
rupt The NMI is usually reserved for important functions
that must be serviced when they occur such as imminent
power failure The programmer can selectively enable or
disable maskable interrupts (INT RSTA RSTB and RSTC)
This selectivity allows the programmer to disable the mask-
able interrupts during periods when timing constraints don’t
allow program interruption
There are two interrupt enable flip-flops (IFF₁ and IFF₂) on
the NSC800 Two instructions control these flip-flops En-
able Interrupt (EI) and Disable Interrupt (DI) The state of
IFF₁ determines the enabling or disabling of the maskable
interrupts while IFF₂ is used as a temporary storage loca-
tion for the state of IFF₁
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