NSC800 Datasheet, PDF (10/76 Pages) National Semiconductor (TI) – NSC800TM High-Performance Low-Power CMOS Microprocessor

8 0 Functional Description
This section reviews the CPU architecture shown below fo-
cusing on the functional aspects from a hardware perspec-
tive including timing details
As illustrated in Figure 1 the NSC800 is an 8-bit parallel
device The major functional blocks are the ALU register
array interrupt control timing and control logic These areas
are connected via the 8-bit internal data bus Detailed de-
scriptions of these blocks ae provided in the following sec-
tions
Note Applicable pinout for 40-pin
dual-in-line package within parentheses
FIGURE 1 NSC800 CPU Functional Block Diagram
TL C 5171 – 9
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