NSC800 Datasheet, PDF (8/76 Pages) National Semiconductor (TI) – NSC800TM High-Performance Low-Power CMOS Microprocessor

NSC800 HARDWARE
6 0 Pin Descriptions
6 1 INPUT SIGNALS
Reset Input (RESET IN) Active low Sets A (8–15) and AD
(0 – 7) to TRI-STATE (high impedance) Clears the con-
tents of PC I and R registers disables interrupts and acti-
vates reset out
Bus Request (BREQ) Active low Used when another de-
vice requests the system bus The NSC800 recognizes
BREQ at the end of the current machine cycle and sets
A(8 – 15) AD(0 – 7) IO M RD and WR to the high imped-
ance state RFSH is high during a bus request cycle The
CPU acknowledges the bus request via the BACK output
signal
Non-Maskable Interrupt (NMI) Active low The non-mask-
able interrupt generated by the peripheral device(s) is the
highest priority interrupt The edge sensitive interrupt re-
quires only a pulse to set an internal flip-flop which gener-
ates the internal interrupt request The NMI flip-flop is moni-
tored on the same clock edge as the other interrupts It
must also meet the minimum set-up time spec for the inter-
rupt to be accepted in the current machine instruction
When the processor accepts the interrupt the flip-flop resets
automatically Interrupt execution is independent of the in-
terrupt enable flip-flop NMI execution results in saving the
PC on the stack and automatic branching to restart address
X’0066 in memory
Restart Interrupts A B C (RSTA RSTB RSTC) Active
low level sensitive The CPU recognizes restarts generated
by the peripherals at the end of the current instruction if
their respective interrupt enable and master enable bits are
set Execution is identical to NMI except the interrupts vec-
tor to the following restart addresses
Name
Restart
Address (X’)
NMI
0066
RSTA
003C
RSTB
0034
RSTC
002C
INTR (Mode 1)
0038
The order of priority is fixed The list above starts with the
highest priority
Interrupt Request (INTR) Active low level sensitive The
CPU recognizes an interrupt request at the end of the cur-
rent instruction provided that the interrupt enable and mas-
ter interrupt enable bits are set INTR is the lowest priority
interrupt Program control selects one of three response
modes which determines the method of servicing INTR in
conjunction with INTA See Interrupt Control
Wait (WAIT) Active low When set low during RD WR or
INTA machine cycles (during the WR machine cycle wait
must be valid prior to write going active) the CPU extends its
machine cycle in increments of t (wait) states The wait ma-
chine cycle continues until the WAIT input returns high
The wait strobe input will be accepted only during machine
cycles that have RD WR or INTA strobes and during the
machine cycle immediately after an interrupt has been ac-
cepted by the CPU The later cycle has its RD strobe sup-
pressed but it will still accept the wait
Power-Save (PS) Active low PS is sampled during the last
t state of the current instruction cycle When PS is low the
CPU stops executing at the end of current instruction and
keeps itself in the low-power mode Normal operation re-
sumes when PS returns high (see Power Save Feature de-
scription)
CRYSTAL (X_IN X_OUT) X_IN can be used as an external
clock input A crystal can be connected across X_IN and
X_OUT to provide a source for the system clock
6 2 OUTPUT SIGNALS
Bus Acknowledge (BACK) Active low BACK indicates to
the bus requesting device that the CPU bus and its control
signals are in the TRI-STATE mode The requesting device
then commands the bus and its control signals
Address Bits 8 – 15 A(8 – 15) Active high These are the
most significant 8 bits of the memory address during a
memory instruction During an I O instruction the port ad-
dress on the lower 8 address bits gets duplicated onto A(8 –
15) During a BREQ BACK cycle the A(8 – 15) bus is in the
TRI-STATE mode
Reset Out (RESET OUT) Active high When RESET OUT
is high it indicates the CPU is being reset This signal is
normally used to reset the peripheral devices
Input Output Memory (IO M) An active high on the IO M
output signifies that the current machine cycle is an input
output cycle An active low on the IO M output signifies that
the current machine cycle is a memory cycle It is TRI-
STATE during BREQ BACK cycles
Refresh (RFSH) Active low The refresh output indicates
that the dynamic RAM refresh cycle is in progress RFSH
goes low during T3 and T4 states of all M1 cycles During
the refresh cycle AD(0 – 7) has the refresh address and
A(8 – 15) indicates the interrupt vector register data RFSH is
high during BREQ BACK cycles
Address Latch Enable (ALE) Active high ALE is active
only during the T1 state of any M cycle and also T3 state of
the M1 cycle The high to low transition of ALE indicates
that a valid memory I O or refresh address is available on
the AD(0 – 7) lines
Read Strobe (RD) Active low The CPU receives data via
the AD(0 – 7) lines on the trailing edge of the RD strobe The
RD line is in the TRI-STATE mode during BREQ BACK cy-
cles
Write Strobe (WR) Active low The CPU sends data via the
AD(0 – 7) lines while the WR strobe is low The WR line is in
the TRI-STATE mode during BREQ BACK cycles
Clock (CLK) CLK is the output provided for use as a sys-
tem clock The CLK output is a square wave at one half the
input frequency
Interrupt Acknowledge (INTA) Active low This signal
strobes the interrupt response vector from the interrupting
peripheral devices onto the AD(0 – 7) lines INTA is active
during the M1 cycle immediately following the t state where
the CPU recognized the INTR interrupt request
Two of the three interrupt request modes use INTA In
mode 0 one to four INTA signals strobe a one to four byte
instruction onto the AD(0 – 7) lines In mode 2 one INTA sig-
nal strobes the lower byte of an interrupt response vector
onto the bus In mode 1 INTA is inactive and the CPU re-
sponse to INTR is the same as for an NMI or restart inter-
rupt
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