NSC800 Datasheet, PDF (55/76 Pages) National Semiconductor (TI) – NSC800TM High-Performance Low-Power CMOS Microprocessor

12 13 CPU Control (Continued)
IM 1
The CPU is placed in interrupt mode 1
No flags affected
76543210
11101101
01010110
Timing
Addressing Mode
M cycles
T states
NA
2
8 (4 4)
IM 2
The CPU is placed in interrupt mode 2
No flags affected
76543210
11101101
01011110
Timing
Addressing Mode
M cycles
T states
NA
2
8 (4 4)
12 14 Program Control
JUMPS
JP nn
Unconditional jump to program location nn
PC w nn
No flags affected
76543210
11000011
n (low-order byte)
n (high-order byte)
Timing
Addressing Mode
M cycles
T states
Direct
3
10 (4 3 3)
JP (ss)
Unconditional jump to program location pointed to by regis-
ter ss
PC w ss
No flags affected
76543210
1 1 1 0 1 0 0 1 JP (HL)
Timing
Addressing Mode
M cycles 1
T states 4
Register Indirect
76 5 43210
1 1 N_X 1 1 1 0 1
JP (IX) (for N_X e 0)
JP (IY) (for N_X e 1)
11 1 01001
Timing
Addressing Mode
M cycles 2
T states 8 (4 4)
Register Indirect
JP cc nn
Conditionally jump to program location nn based on testable
flag states
If cc true
No flags affected
PC w nn
otherwise continue
765 4 3210
11
cc
010
n (low-order byte)
n (high-order byte)
Timing
Addressing Mode
M cycles
T states
Direct
3
10 (4 3 3)
JR d
Unconditional jump to program location calculated with re-
spect to the program counter and the displacement d
PC w PC a d
No flags affected
76543210
00011000
db2
Timing
Addressing Mode
M cycles 3
T states 12 (4 3 5)
PC Relative
JR kk d
Conditionally jump to program location calculated with re-
spect to the program counter and the displacement d
based on limited testable flag states
If kk true
No flags affected
PC w PC a d
otherwise continue
76543210
0 0 1 kk 0 0 0
db2
Timing if kk met
(true)
if kk not met
(not true)
Addressing Mode
M cycles 3
T states 12 (4 3 5)
M cycles 2
T states 7 (4 3)
PC Relative
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