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NSC800 Datasheet, PDF (37/76 Pages) National Semiconductor (TI) – NSC800TM High-Performance Low-Power CMOS Microprocessor
12 6 8-Bit Arithmetic (Continued)
76543210
10100
r
Timing
Addressing Mode
M cycles 1
T states 4
Source Register
Destination Implied
OR r
Logically OR the contents of the r register and the Accumu-
lator
AwA r
S Set if result is negative
Z Set if result is zero
H Reset
P V Set if result parity is even
N Reset
C Reset
76543210
10110
r
Timing
Addressing Mode
M cycles 1
T states 4
Source Register
Destination Implied
XOR r
Logically exclusively OR the contents of the r register with
the Accumulator
w A
AZr
S Set if result is negative
Z Set if result is zero
H Reset
P V Set if result parity is even
N Reset
C Reset
76543210
10101
r
Timing
Addressing Mode
M cycles 1
T states 4
Source Register
Destination Implied
INC r
Increment register r
rwra1
S Set if result is negative
Z Set if result is zero
H Set if carry from bit 3
P V Set only if r was X’7F before
operation
N Reset
CNA
76543210
00
r
100
Timing
Addressing Mode
M cycles 1
T states 4
Source Register
Destination Register
CP r
Compare the contents of register r with the Accumulator
and set the flags accordingly
Abr
S Set if result is negative
Z Set if result is zero
H Set if borrow from bit 4
P V Set if result exceeds 8-bit 2’s
complement range
N Set
C Set according to borrow
76543210
10111
r
Timing
Addressing Mode
M cycles 1
T states 4
Source Register
Destination Implied
DEC r
Decrement the contents of register r
rwrb1
S Set if result is negative
Z Set if result is zero
H Set according to a borrow from
bit 4
P V Set only if r was X’80 prior to
operation
N Set
CNA
76543210
00
r
101
Timing
Addressing Mode
M cycles 1
T states 4
Source Register
Destination Register
CPL
Complement the Accumulator (1’s complement)
AwA
SNA
ZNA
H Set
PVNA
N Set
CNA
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