NSC800 Datasheet, PDF (38/76 Pages) National Semiconductor (TI) – NSC800TM High-Performance Low-Power CMOS Microprocessor

12 6 8-Bit Arithmetic (Continued)
76543210
00101111
Timing
Addressing Mode
M cycles 1
T states 4
Implied
NEG
Negate the Accumulator (2’s complement)
Aw0bA
S Set if result is negative
Z Set if result is zero
H Set according to borrow from
bit 4
P V Set only if Accumulator was
X’80 prior to operation
N Set
C Set only if Accumulator was not
X’00 prior to operation
76543210
11101101
01000100
Timing
Addressing Mode
M cycles 2
T states 8 (4 4)
Implied
CCF
Complement the carry flag
CY w CY
SNA
ZNA
H Previous carry
PVNA
N Reset
C Complement of previous carry
76543210
00111111
Timing
Addressing Mode
M cycles 1
T states 4
Implied
SCF
Set the carry flag
CY w 1
SNA
ZNA
H Reset
PVNA
N Reset
C Set
76543210
00110111
Timing
Addressing Mode
M cycles 1
T states 4
Implied
DAA
Adjust the Accumulator for BCD addition and subtraction
operations To be executed after BCD data has been oper-
ated upon the standard binary ADD ADC INC SUB SBC
DEC or NEG instructions (see ‘‘Register Addressing Arith-
metic’’ table)
S Set according to bit 7 of result
Z Set if result is zero
H Set according to instructions
P V Set according to parity of result
NNA
C Set according to instructions
76543210
00100111
Timing
Addressing Mode
M cycles 1
T states 4
Implied
IMMEDIATELY ADDRESSED ARITHMETIC
ADD A n
Add the immediate data n to the Accumulator
AwAan
S Set if result is negative
Z Set if result is zero
H Set if carry from bit 3
P V Set if result exceeds 8-bit 2’s
complement range
N Reset
C Set if carry from bit 7
76543210
11000110
n
Timing
Addressing Mode
M cycles 2
T states 7 (4 3)
Source Immediate
Destination Implied
ADC A n
Add with carry the immediate data n and the Accumulator
w A
A a n a CY S Set if result is negative
Z Set if result is zero
H Set if carry from bit 3
P V Set if result exceeds 8-bit 2’s
complement range
N Reset
C Set according to carry from bit
7
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