MC68306FC16 Datasheet, PDF (99/191 Pages) Motorola, Inc – Integrated EC000 Processor

NOTE
Unused chip selects must be disabled to prevent interference
with other chip selects, DRAM, or externally decoded
resources.
There are three ways to disable a chip select, corresponding to the three match
conditions:
1. All CSFCx bits are zero
2. Both CSW/CSR are zero
3. Any unused CSAx bit is one.
Chip selects 7 through 4 are still matched even if running in address mode (AMODE = 0).
They can be disabled, or they can be used to provide automatic DTACK timing for
externally decoded resources.
If more decodes are necessary than are supplied on the MC68306, one of the existing
chip selects should be used (Figure 5-1) to enable the external decoding, since some
signals used to qualify the chip selects are not available externally.
The registers listed below allow the base address, range, and cycle duration of each chip
select to be independently programmed. The chip select configuration registers do not
support byte writes. The registers can be written as either 16-bit or 32-bit, but 32-bit
accesses are preferred. Any write access affects all 16 bits of the high half or low half
register. Only chip select 0 is affected by reset.
5.2.6.1 CHIP SELECT CONFIGURATION REGISTERS (HIGH HALF)
FFFFFFC0 (CS0)
15
14
13
CSA31 CSA3 CSA2
0
9
RESE
T:
0
0
0
12
CSA2
8
0
11
CSA2
7
0
10
CSA2
6
0
9
CSA2
5
0
8
CSA2
4
0
7
CSA2
3
0
6
5
CSA22 CSA21
0
0
4
CSA20
0
3
CSA19
0
2
1
CSA18 CSA17
0
CSW
0
0
1
SUPERVISOR ONLY
FFFFFFDC (CS7), FFFFFFD8 (CS6), FFFFFFD4 (CS5), FFFFFFD0 (CS4), FFFFFFCC (CS3), FFFFFFC8 (CS2),
FFFFFFC4 (CS1)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CSA31 CSA3 CSA2 CSA2 CSA2 CSA2 CSA2 CSA2 CSA2 CSA22 CSA21 CSA20 CSA19 CSA18 CSA17 CSW
0
9
8
7
6
5
4
3
RESE
T:
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
SUPERVISOR ONLY
CSA31–CSA17—Chip Select Address
This bit field selects the base address for each chip select.
MOTOROLA
MC68306 USER'S MANUAL
5-9