MC68306FC16 Datasheet, PDF (43/191 Pages) Motorola, Inc – Integrated EC000 Processor

STATE 17 During S17, no bus signals are altered.
STATE 18 During S18, no bus signals are altered.
STATE 19 During S19, no bus signals are altered.
STATE 20 During S20. no bus signals are altered.
STATE 21 The processor negates AS and UDS /LDS.
3.1.4 CPU Space Cycle
A CPU space cycle, indicated when the function codes are all high, is a special processor
cycle. In the 68EC000 core, CPU space is used only for interrupt acknowledge cycles.
Figure 3-10 shows the encoding of an interrupt acknowledge cycle.
INTERRUPT
ACKNOWLEDGE
1 11
31
3 10
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LEVEL 1
Figure 3-10. Interrupt Acknowledge Cycle
The interrupt acknowledge cycle places the level of the interrupt being acknowledged on
address bits A3–A1 and drives all other address lines high. The interrupt acknowledge
cycle reads a vector number when the device places a vector number on the data bus.
The timing diagram for an interrupt acknowledge cycle is shown in Figure 3-11.
MOTOROLA
MC68306 USER'S MANUAL
3-11