MC68306FC16 Datasheet, PDF (119/191 Pages) Motorola, Inc – Integrated EC000 Processor

RxD
RECEIVER
ENABLED
RxRDY
(SR0)
FFULL
(SR1)
C1
C2
C3
C4
C5
C6
C7
C8
C6, C7, C8 ARE LOST
CS
OVERRUN
(SR4)
RR
STATUS DATA
C1
C5
LOST
R R R R RR
STATUS DATA STATUS _DATA STATUS DATA
C2
C3
C4
1
RTS
(OP0)
RESET BY COMMAND
OPR(0) = 1
NOTES:
1. Timing shown for MR1(7) = 1
2. Timing shown for OPCR(4) = 1 and MR1(6) = 0
3. R = Read
4. C_N = Received Character
Figure 6-6. Receiver Timing Diagram
The receiver detects the beginning of a break in the middle of a character if the break
persists through the next character time. When the break begins in the middle of a
character, the receiver places the damaged character in the receiver first-in-first-out
(FIFO) stack and sets the corresponding error conditions and RxRDY bit in the DUSR.
Then, if the break persists until the next character time, the receiver places an all-zero
character into the receiver FIFO and sets the corresponding RB and RxRDY bits in the
DUSR.
6.3.2.3 FIFO STACK. The FIFO stack is used in each channel's receiver buffer logic. The
stack consists of three receiver holding registers. The receive buffer consists of the FIFO
and a receiver shift register connected to the RxDx (refer to Figure 6-4). Data is
assembled in the receiver shift register and loaded into the top empty receiver holding
MOTOROLA
MC68306 USER'S MANUAL
6-11