MC68306FC16 Datasheet, PDF (44/191 Pages) Motorola, Inc – Integrated EC000 Processor

IPL2–IPL0 VALID INTERNALLY
IPL2–IPL0 SAMPLED
IPL2–IPL0 TRANSITION
S0 S1 S2 S3 S4 S5 S6 S7
CLK
FC2–FC0
A23–A4
A3–A1
AS
UDS*
LDS
IACK
S0 S1 S2 S3 S4 SW SW S5 S6 S7 S0 S1 S2 S3 S4 S5 S6
R/W
DTACK
D15–D8
D7–D0
IPL2–IPL0
LAST BUS CYCLE OF INSTRUCTION
(READ OR WRITE)
STACK
PCL
(SSP)
IACK CYCLE
(VECTOR NUMBER
ACQUISITION)
STACK AND
VECTOR
FETCH
*_{Although a vector number is one byte, both data strobes are asserted due to the microcode used for exception processing. The processor does not}
recognize anything on data lines D8 through D15 at this time.
Figure 3-11. Interrupt Acknowledge Cycle Timing Diagram
3.2 BUS ARBITRATION
Bus arbitration is a technique used by bus master devices to request, to be granted, and
to acknowledge bus mastership. Bus arbitration consists of the following:
1. Asserting a bus mastership request
2. Receiving a grant indicating that the bus is available at the end of the current cycle
3. Acknowledging that mastership has been assumed
Figure 3-12 is a flowchart showing the bus arbitration cycle of the EC000 core. Figure 3-
13 is a timing diagram of the bus arbitration cycle charted in Figure 3-12. This technique
allows processing of bus requests during data transfer cycles.
3-12
MC68306 USER'S MANUAL
MOTOROLA