MC68306FC16 Datasheet, PDF (50/191 Pages) Motorola, Inc – Integrated EC000 Processor

When a bus request is made after the MPU has begun a bus cycle and before AS has
been asserted (S0), the special sequence shown in Figure 3-20 applies. Instead of being
asserted on the next rising edge of clock, BG is delayed until the second rising edge
following its internal assertion.
RA
RA ¹
GT
XA1
RA
GT
RA
XX
XA
GT
RA
RA
RA
RA
R+A
GT
GT
RX
RA
RA
GT
GT
XX
RA
(a) 3-Wire Bus Arbitration
R
R
GT
STATE 0
R
GT
STATE 1
R
GT
STATE 4
X
GT
STATE 2
GT
X
STATE 3
R
(b) 2-Wire Bus Arbitration
R
R = Bus Request Internal
A = Bus Grant Acknowledge Internal
G = Bus Grant
T = Three-state Control to Bus Control Logic
X = Don't Care
Notes:
1. State machine will not change if
the bus is S0 or S1. Refer to
BUS ARBITRATION CONTROL. 5.2.3.
2. The address bus will be placed in
the high-impedance state if T is
asserted and AS is negated.
Figure 3-17. Bus Arbitration Unit State Diagrams
3-18
MC68306 USER'S MANUAL
MOTOROLA