MC68306FC16 Datasheet, PDF (169/191 Pages) Motorola, Inc – Integrated EC000 Processor

EXTAL
3.8 V
1.5 V
0.8 V
4
1A
CLKOUT
1.5 V
1
2
3
5
2A
1.5 V
1
3A
1.5 V
3.8 V
1.5 V
0.8 V
1A
1.5 V
NOTE: Timing measurements are referenced to and from a low voltage of 0.8 V and a high
voltage of 3.8 V, unless otherwise noted. The voltage swing through this range
should start outside and pass through the range such that the rise or fall will be linear
between 0.8 V and 3.8 V.
Figure 8-2. Clock Output Timing
8.7 AC ELECTRICAL SPECIFICATIONS—READ AND WRITE
CYCLES (The electrical specifications in this document are preliminary; see Figures 8-3 and 8-4)
16.67 MHz
Num
Characteristic
Min Max Unit
6 CLKOUT Low to Address Valid (Row Address for DRAM Cycle) — 30 ns
6A CLKOUT High to FC Valid
— 30 ns
7 CLKOUT High to Data Bus High Impedance (Maximum)
— 50 ns
8 CLKOUT High to Address, FC Invalid (Minimum)
9¹ CLKOUT High to AS, LDS, UDS Asserted
0
— ns
3 30 ns
9A
11²
11A²
12¹
UDS, LDS Asserted to OE, UW, LW Asserted
Address Valid to AS, LDS, UDS Asserted (Read)/ AS Asserted
(Write)
FC Valid to AS, LDS, UDS Asserted (Read)/ AS, Asserted
(Write)
CLKOUT Low to AS, LDS, UDS Negated
0 15 ns
15 — ns
45 — ns
3 30 ns
12A
13²
14²
14A²
15²
UDS, LDS Negated to OE, UW, LW Negated
AS, LDS, UDS Negated to Address, FC Invalid
AS (and LDS, UDS Read) Width Asserted
LDS, UDS, Width Asserted (Write)
AS, LDS, UDS Width Negated
0 15 ns
15 — ns
120 — ns
50 — ns
60 — ns
16 CLKOUT High to Control Bus High Impedance
17² AS, LDS, UDS Negated to R/W Invalid
18¹ CLKOUT High to R/W High (Read)
20¹ CLKOUT High to R/W Low (Write)
— 50 ns
15 — ns
0 30 ns
0 30 ns
MOTOROLA
MC68306 USER'S MANUAL
8-5