MC68306FC16 Datasheet, PDF (71/191 Pages) Motorola, Inc – Integrated EC000 Processor

The status register, illustrated in Figure 4-2, contains the interrupt mask (eight levels
available) and the following condition codes: overflow (V), zero (Z), negative (N), carry (C),
and extend (X). Additional status bits indicate that the processor is in the trace (T) mode
and/or in the supervisor (S) state.
SYSTEM BYTE
USER BYTE
(CONDITION CODE REGISTER)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
T 0 S 0 0 I2 I1 I0 0 0 0 X N Z V C
TRACE MODE
SUPERVISOR/USER STATE
INTERRUPT
PRIORITY MASK
EXTEND
NEGATIVE
ZERO
OVERFLOW
CARRY
EC2
Figure 4-2. Status Register
4.3.1 Data Format Summary
The processor supports the basic data formats of the M68000 family. The instruction set
supports operations on other data formats such as memory addresses.
The operand data formats supported by the integer unit (IU) are the standard twos-
complement data formats defined in the M68000 family architecture. Registers, memory,
or instructions themselves can contain IU operands. The operand size for each instruction
is either explicitly encoded in the instruction or implicitly defined by the instruction
operation. Table 4-1 lists the data formats for the processor. Refer to M68000PM/AD,
M68000 Family Programmer’s Reference Manual, for details on data format organization
in registers and memory.
Table 4-1. Processor Data Formats
Operand Data Format
Bit
Binary-Coded Decimal (BCD)
Byte Integer
Word Integer
Long-Word Integer
Size
1 Bit
8 Bits
8 Bits
16 Bits
32 Bits
Notes
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Packed: 2 Digits/Byte; Unpacked: 1 Digit/Byte
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MOTOROLA
MC68306 USER'S MANUAL
4-3