MC68306FC16 Datasheet, PDF (100/191 Pages) Motorola, Inc – Integrated EC000 Processor

CSW—Chip Select Write
This bit determines whether write cycles are permitted to chip select space. If read and
write cycles are both inhibited, chip select is inhibited.
0 = Write cycles are inhibited to chip select space
1 = Write cycles are permitted to chip select space
5.2.6.2 CHIP SELECT CONFIGURATION REGISTERS (LOW HALF)
FFFFFFC2 (CS0)
15
14
13
12
CSR CSFC CSFC —
6
5
RESE
T:
1
1
1
0
11
10
9
8
7
6
5
4
3
2
1
0
— CSFC CSFC — CSM3 CSM2 CSM1 CSM0 CSDT3 CSDT2 CSDT CSDT
2
1
1
0
1
1
1
1
0
0
0
0
1
1
1
0
SUPERVISOR ONLY
FFFFFFDE (CS7), FFFFFFDA (CS6), FFFFFFD6 (CS5), FFFFFFD2 (CS4), FFFFFFCE (CS3), FFFFFFCA (CS2),
FFFFFFC6 (CS1)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CSR CSFC CSFC —
6
5
— CSFC CSFC — CSM3 CSM2 CSM1 CSM0 CSDT3 CSDT2 CSDT CSDT
2
1
1
0
RESE
T:
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
SUPERVISOR ONLY
CSR—Chip Select Read
This bit determines whether read cycles are permitted to chip select space. If read and
write cycles are both inhibited, chip select is inhibited.
0 = Read cycles are inhibited to chip select space
1 = Read cycles are permitted to chip select space
CSFC 6, 5, 2, 1—Chip Select Function Code Enable
This bit determines which function code accesses are permitted to chip select space. If
all function code cycles are inhibited, chip select is inhibited.
0 = Function code ‘n’ cycles are inhibited to chip select space
1 = Function code ‘n’ cycles are permitted to chip select space
CSM3–0—Chip Select Address Match
This field determines which chip select bits must match address bits for chip select to
occur. CSA bits not included in match must be set to zero, or else this chip select is
inhibited.
0000 =
0001 =
0010 =
A31–A17 ignored in chip select address match
A31 must match CSA31; A30–A17 ignored in chip select address match
A31–A30 must match CSA31–CSA30; A29–A17 ignored in chip select
address match
5-10
MC68306 USER'S MANUAL
MOTOROLA