MC68306FC16 Datasheet, PDF (53/191 Pages) Motorola, Inc – Integrated EC000 Processor

BUS THREE-STATED
BG ASSERTED
BR VALID INTERNAL
BR SAMPLED
BR ASSERTED
BUS RELEASED FROM THREE STATE AND
PROCESSOR STARTS NEXT BUS CYCLE
BGACK NEGATED INTERNAL
BGACK SAMPLED
BGACK NEGATED
CLK
S0 S2 S4 S6
BR
BG
S0 S2 S4 S6 S0
BGACK
FC2–FC0
A31–A1
AS
UDS
LDS
R/W
DTACK
D15–D0
PROCESSOR
ALTERNATE BUS MASTER
PROCESSOR
Figure 3-20. Three-Wire Bus Arbitration Timing Diagram—Special Case
MOTOROLA
MC68306 USER'S MANUAL
3-21