MC68306FC16 Datasheet, PDF (33/191 Pages) Motorola, Inc – Integrated EC000 Processor

SECTION 3
68000 BUS OPERATION DESCRIPTION
This section describes control signal and bus operation during data transfer operations,
bus arbitration, bus error and halt conditions, and reset operation.
NOTE
The terms assertion and negation are used extensively in this
manual to avoid confusion when describing a mixture of
"active-low" and "active-high" signals. The term assert or
assertion is used to indicate that a signal is active or true,
independently of whether that level is represented by a high or
low voltage. The term negate or negation is used to indicate
that a signal is inactive or false.
3.1 DATA TRANSFER OPERATIONS
Transfer of data between devices involves the following signals:
1. Address bus A1 through A31
2. Data bus D0 through D7 and/or D8 through D15
3. Control signals
The address and data buses are separate parallel buses used to transfer data using an
asynchronous bus structure. In all cases, the bus master must deskew all signals it issues
at both the start and end of a bus cycle. In addition, the bus master must deskew the
acknowledge and data signals from the slave device.
The following paragraphs describe the read, write, read-modify-write, and CPU space
cycles. The indivisible read-modify-write cycle implements interlocked multiprocessor
communications. A CPU space cycle is a special processor cycle.
3.1.1 Read Cycle
During a read cycle, the processor receives either one or two bytes of data from the
memory or from a peripheral device. If the instruction specifies a word or long-word
operation, the processor reads both upper and lower bytes simultaneously by asserting
both upper and lower data strobes. A long-word read is accomplished by two consecutive
word reads. When the instruction specifies byte operation, the processor uses the internal
A0 bit to determine which byte to read and issues the appropriate data strobe. When A0 is
zero, the upper data strobe is issued; when A0 is one, the lower data strobe is issued.
When the data is received, the processor internally positions the byte appropriately.
MOTOROLA
MC68306 USER'S MANUAL
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