MC68306FC16 Datasheet, PDF (162/191 Pages) Motorola, Inc – Integrated EC000 Processor

MC68306 includes a 3-bit instruction register without parity, consisting of a shift register
with three parallel outputs. Data is transferred from the shift register to the parallel outputs
during the update-IR controller state. The three bits are used to decode the six unique
instructions listed in Table 7-3.
The parallel output of the instruction register is reset to 001 in the test-logic-reset
controller state. Note that this preset state is equivalent to the ID instruction.
Table 7-3. Instructions
Code
B2 B1 B0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Instruction
EXTEST
ID
BYPASS
CLAMP
MODULE MODE
BYPASS
SAMPLE/PRELOAD
BYPASS
During the capture-IR controller state, the parallel inputs to the instruction shift register are
loaded with the 3-bit binary value (001). The parallel outputs, however, remain unchanged
by this action since an update-IR signal is required to modify them.
7.4.1 EXTEST (000)
The external test (EXTEST) instruction selects the 124-bit boundary scan register.
EXTEST asserts internal reset for the MC68306 system logic to force a predictable benign
internal state while performing external boundary scan operations.
By using the TAP, the register is capable of a) scanning user-defined values into the
output buffers, b) capturing values presented to input pins, c) controlling the direction of
bidirectional pins, and d) controlling the output drive of three-state output pins. For more
details on the function and uses of EXTEST, please refer to the IEEE 1149.1 document.
7.4.2 SAMPLE/PRELOAD (110)
The SAMPLE/PRELOAD instruction selects the 124-bit boundary scan register and
provides two separate functions. First, it provides a means to obtain a snapshot of system
data and control signals. The snapshot occurs on the rising edge of TCK in the capture-
DR controller state. The data can be observed by shifting it transparently through the
boundary scan register.
7-10
MC68306 USER'S MANUAL
MOTOROLA