MC68306FC16 Datasheet, PDF (32/191 Pages) Motorola, Inc – Integrated EC000 Processor

2.6.9 Crystal Oscillator (X1/CLK, X2)
These two pins are the connections for an external crystal to the internal oscillator circuit.
If an external oscillator is used, it should be connected to X1/CLK, with X2 left floating,
and must drive CMOS levels. A crystal or clock input must be supplied at all times.
2.6.10 IP2
This input can be used as a general-purpose input, the channel B receiver external clock
input (RxCB), or the counter/timer external clock input. When this input is used as the
external clock by the receiver, the received data is sampled on the rising edge of the
clock. A change-of-state detector is also associated with this input.
2.6.11 OP3
This output can be used as a general-purpose output, the open-drain active low counter-
ready output, the open-drain timer output, the channel B transmitter 1X-clock output, or
the channel B receiver 1X-clock output.
2.7 JTAG PORT TEST SIGNALS
The following signals are used with the on-chip test logic defined by the IEEE 1149.1
standard. See IEEE 1149.1 Test Access Port for more information on the use of these
signals.
2.7.1 Test Clock (TCK)
This input provides a clock for on-chip test logic defined by the IEEE 1149.1 standard.
2.7.2 Test Mode Select (TMS)
This input controls test mode operations for on-chip test logic defined by the IEEE 1149.1
standard. Connecting TMS to VCC disables the test controller, making all JTAG circuits
transparent to the system.
2.7.3 Test Data In (TDI)
This input is used for serial test instructions and test data for on-chip test logic defined by
the IEEE 1149.1 standard.
2.7.4 Test Data Out (TDO)
This output is used for serial test instructions and test data for on-chip test logic defined by
the IEEE 1149.1 standard.
2.7.5 Test Reset (TRST )
This input is the master reset for on-chip test logic defined by the IEEE 1149.1 standard.
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