MC68306FC16 Datasheet, PDF (179/191 Pages) Motorola, Inc – Integrated EC000 Processor

CLKOUT
FC0–FC2
A15/DRAMA 14–
A1/DRAMA 0
AS
UDS, LDS
R/W
UW, LW
OE
92
DTACK
D15–D0
DRAMW
RAS
80
79
CAS
90
91
* NOTE: TAS IS A BYTE-ONLY INSTRUCTION, THEREFORE ONLY ONE OF UW, LW AND ONLY ONE CAS WILL BE ASSERTED.
Figure 8-11. DRAM Timing – 1-Wait, Test and Set
8.11 SERIAL MODULE ELECTRICAL CHARACTERISTICS
(TA = 0 °C to 70 °C, V _CC = 5.0 V ±5%, See Note 1)
Characteristic
Symbol Min Max Unit
X1/CLK Input Leakage Current
IX1L
2.5
µA
X1/CLK Frequency (see Note 2)
fCLK
2.0
4.0 MHz
Counter/Timer Clock Frequency (IP2)
fCTC
0 16.67 MHz
NOTES:
1. All voltage measurements are referenced to ground (GND). For testing, all input signals except X1/CLK swing
between 0.4 V and 2.4 V with a maximum transition time of 20 ns. For X1/CLK, this swing is between 0.4 V and
4.4 V. All time measurements are referenced at input and output voltages of 0.8 V and 2.0 V as appropriate.
Test conditions for outputs: CL = 150 pF, R _L = 750 Ω to VCC .
2. To use the standard baud rates selected by the clock-select register given in Tables 6-5 and 6-6, the X1/CLK
frequency should be set to 3.6864 MHz or a 3.6864 MHz crystal should be connected across pins X1/CLK and X2.
3. IP5–2 for RxC, TxC are not supported in the MC68306.
MOTOROLA
MC68306 USER'S MANUAL
8-15