MC68306FC16 Datasheet, PDF (103/191 Pages) Motorola, Inc – Integrated EC000 Processor

68306 regains bus ownership. Only one refresh cycle occurs after bus ownership is
regained, regardless of the time the bus was granted away.
The DRAM controller provides RAS/CAS timing, 15 multiplexed address bits, and refresh
timing. All DRAM accesses are either zero or one wait state cycles, unless delayed by a
refresh. Zero wait state operation supports DRAMs up to 80 ns RAS access, and one wait
state cycles supports DRAMs up to 120 ns RAS access (at 16.67 MHz). External DTACK
is not allowed on DRAM accesses. A refresh can add up to three extra wait-states to zero
wait-state accesses or 4 extra wait-states to one-wait state accesses. Read-modify-write
cycles to DRAM use page mode, and the write portion is always zero wait-state,
regardless of the DRDT bit setting.
The organization of external DRAM is one or two banks, by two bytes. CAS0 controls the
high byte (D15–D8) and CAS1 controls the low byte (D7–D0).
The minimum bank size is 128 Kbytes (64K × 2 bytes), because of the address
multiplexer, shown in Table 5-3.
Value Of:
DRAMA14
DRAMA13
DRAMA12
DRAMA11
DRAMA10
DRAMA9
DRAMA8
DRAMA7
DRAMA6
DRAMA5
DRAMA4
DRAMA3
DRAMA2
DRAMA1
DRAMA0
Table 5-3. DRAM Address Multiplexer
At RAS When DRSZ2–0 Is:
111 110 101 100 011 010 001
A30 A29 A28 A27 A26 A25 A24
A29 A28 A27 A26 A25 A24 A23
A28 A27 A26 A25 A24 A23 A22
A27 A26 A25 A24 A23 A22 A21
A26 A25 A24 A23 A22 A21 A20
A25 A24 A23 A22 A21 A20 A19
A24 A23 A22 A21 A20 A19 A18
A23 A22 A21 A20 A19 A18 A17
A22 A21 A20 A19 A18 A17 A16
A21 A20 A19 A18 A17 A16 A15
A20 A19 A18 A17 A16 A15 A14
A19 A18 A17 A16 A15 A14 A13
A18 A17 A16 A15 A14 A13 A12
A17 A16 A15 A14 A13 A12 A11
A16 A15 A14 A13 A12 A11 A10
At CAS:
000
A23
A15
A22
A14
A21
A13
A20
A12
A19
A11
A18
A10
A17
A9
A16
A8
A15
A7
A14
A6
A13
A5
A12
A4
A11
A3
A10
A2
A9
A1
Because the DRAM address multiplexer provides contiguous address bits to the full 15-bit
DRAMA bus width during RAS, more banks can be supported by externally decoding bits
beyond the RAS address width of the DRAMs. If this is done, the DRAMA, CAS, and
DRAMW signals should be buffered. This will almost certainly require the wait state. Also,
DRAMs with more row address pins than column address pins are supported.
MOTOROLA
MC68306 USER'S MANUAL
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