MC68306FC16 Datasheet, PDF (95/191 Pages) Motorola, Inc – Integrated EC000 Processor

Where:
EXTAL is the crystal period in nanoseconds and period is in nanoseconds.
5.2.4 Interrupt Registers
Up to seven prioritized external interrupts can be supported by programming the following
registers. More interrupt sources can be supported by external daisy-chaining. The
interrupt inputs are internally synchronized. Edge-triggered interrupts are not supported.
Each interrupt can be either active-high or active-low. The active level is self-programmed
during reset, with no software intervention. Every interrupt must be at its inactive level at
the end of reset. Each interrupt can be enabled or disabled by programming the
corresponding bit in the interrupt control register.
Each interrupt can be auto-vectored, by programming the interrupt control register. Auto-
vectored interrupt acknowledge cycles are zero wait states. If no active interrupt is present
at the level being acknowledged, the MC68306 automatically generates a spurious
interrupt vector, which is a zero wait state. Interrupt input synchronization is frozen during
an interrupt acknowledge cycle, so the acknowledge can safely be used to automatically
negate the interrupt.
5.2.4.1 INTERRUPT CONTROL REGISTER
FFFFFFFA/B
15
14
IENT IEN7
13
IEN6
12
IEN5
11
IEN4
10
IEN3
9
IEN2
8
IEN1
RESE
T:
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
— AVEC AVEC6 AVEC5 AVEC4 AVEC3 AVEC AVEC
7
2
1
1
1
1
1
1
1
1
1
SUPERVISOR ONLY
IENT—Timer Interrupt Enable
This bit enables the DUART timer interrupt.
0 = Interrupts disabled.
1 = Interrupts enabled.
IEN7–1—Interrupt Enable 7 through 1
These bits enable interrupt 7, 6, 5, 4, 3, 2, and 1.
0 = Interrupt disabled.
1 = Interrupt enabled.
AVEC7–1—Autovector Enable 7 through 1
These bits enable autovectoring for interrupts 7, 6, 5, 4, 3, 2, and 1.
0 = No autovector.
MOTOROLA
MC68306 USER'S MANUAL
5-5