MC68306FC16 Datasheet, PDF (64/191 Pages) Motorola, Inc – Integrated EC000 Processor

In a pseudo-asynchronous system, timing specifications allow DTACK to be asserted for a
read cycle before the data from a slave device is valid. The length of time that DTACK
may precede data is specified as parameter #31. This parameter must be met to ensure
the validity of the data latched into the processor. No maximum time is specified from the
assertion of AS to the assertion of DTACK. During this unlimited time, the processor
inserts wait cycles in one-clock-period increments until DTACK is recognized. Figure 3-30
shows the important timing parameters for a pseudo-asynchronous read cycle.
ADDR
11
AS
17
R/W
UDS/LDS
DATA
DTACK
A
31
28
29
Figure 3-30. Pseudo-Asynchronous Read Cycle
During a write cycle, after the processor asserts AS but before driving the data bus, the
processor drives R/W low. Parameter #55 specifies the minimum time between the
transition of R/W and the driving of the data bus, which is effectively the maximum turnoff
time for any device driving the data bus.
After the processor places valid data on the bus, it asserts the data strobe signal(s). A
data setup time, similar to the address setup time previously discussed, can be used to
improve performance. Parameter #26 is the minimum time a slave device can accept valid
data before recognizing a data strobe. The slave device asserts DTACK after it accepts
the data. Parameter #25 is the minimum time after negation of the strobes during which
the valid data remains on the address bus. Parameter #28 is the maximum time between
the negation of the strobes by the processor and the negation of DTACK by the slave
device. If DTACK remains asserted past the time specified by parameter #28, the
processor may recognize it as being asserted early in the next bus cycle and may
terminate that cycle prematurely. Figure 3-31 shows the important timing specifications for
a pseudo-asynchronous write cycle.
3-32
MC68306 USER'S MANUAL
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