MC68306FC16 Datasheet, PDF (67/191 Pages) Motorola, Inc – Integrated EC000 Processor

On the rising edge of the clock, at the end of S7 (which may be the start of
S0 for the next bus cycle), the processor places the address bus in the
high-impedance state. During a write cycle, the processor also places the
data bus in the high-impedance state and drives R/W high. External logic
circuitry should respond to the negation of the AS and UDS /LDS by negating
DTACK and/or BERR . Parameter #28 is the hold time for DTACK, and
parameter #30 is the hold time for BERR .
Figure 3-32 shows a synchronous read cycle and the important timing parameters that
apply. The timing for a synchronous read cycle, including relevant timing parameters, is
shown in Figure 3-33.
CLOCK
ADDR
AS
S0
S1
S2
S3
S4
S5
S6
S7
S0
6
9
UDS/LDS
R/W
DTACK
DATA
18
47
27
Figure 3-32. Synchronous Read Cycle
MOTOROLA
MC68306 USER'S MANUAL
3-35