MC68306FC16 Datasheet, PDF (171/191 Pages) Motorola, Inc – Integrated EC000 Processor

CLKOUT
FC2–FC0
A23–A1
AS
LDS / UDS
R/W
S0 S1 S2 S3 S4 S5 S6 S7
6A
8
6
15
14
13
11
11A
9
12
12A
OE
DTACK
DATA IN
BERR / BR
(NOTE 2)
HALT / RESET
ASYNCHRONOUS
INPUTS
(NOTE 1)
9A
47
27
48
31
47
47
47
32
32
56
47
28
29
29A
30
NOTES:
1. Setup time (#47) for asynchronous inputs (HALT, RESET, BR, BGACK, DTACK, BERR, IRQx) guarantees
their recognition at the next falling edge of the clock.
2. BR need fall at this time only to ensure being recognized at the end of the bus cycle.
Figure 8-3. Read Cycle Timing Diagram
MOTOROLA
MC68306 USER'S MANUAL
8-7