MC68306FC16 Datasheet, PDF (139/191 Pages) Motorola, Inc – Integrated EC000 Processor

Table 6-10. Counter/Timer Mode and Source Select Bits
MISC2
0
0
0
0
1
1
1
1
MISC1
0
0
1
1
0
0
1
1
MISC0
0
1
0
1
0
1
0
1
Mode Command
Counter
Counter
Counter
Counter
Timer
Timer
Timer
Timer
Clock Source Select Command
External–IP2
TxCA
TxCB
Crystal or External Clock
External–IP2
External–IP2 Divided by 16
Crystal or External Clock
External Clock Divided by 16
IEC2, IEC1, IEC0—Input Enable Control
1 = DUISR bit 7 will be set and an interrupt will be generated when the
corresponding bit in the DUIPCR (COS2, COS1, or COS0) is set by an external
transition on the IPx input (if bit 7 of the interrupt mask register (DUIMR) is set to
enable interrupts).
0 = Setting the corresponding bit in the DUIPCR has no effect on DUISR bit 7.
6.4.1.10 INTERRUPT STATUS REGISTER (DUISR). The DUISR provides status for all
potential interrupt sources. The contents of this register are masked by the DUIMR. If a
flag in the DUISR is set and the corresponding bit in DUIMR is also set, the IRQ output is
asserted. If the corresponding bit in the DUIMR is cleared, the state of the bit in the
DUISR has no effect on the output.
NOTE
The IDUMR does not mask reading of the DUISR. True status
is provided regardless of the contents of DUIMR. The contents
of DUISR are cleared when the serial module is reset.
DUISR
7
6
5
4
3
2
1
0
COS
DBB
RxRDYB TxRDYB CTR/TM
R
_RDY
DBA RxRDYA TxRDYA
RESET:
0
0
0
0
1
0
0
0
Read Only
COS—Change-of-State
1 = A change-of-state has occurred at one of the IPx inputs and has been selected to
cause an interrupt by programming bit 2, 1 and/or bit 0 of the DUACR.
0 = No selected COSx in the DUIPCR.
MOTOROLA
MC68306 USER'S MANUAL
6-31