MC68306FC16 Datasheet, PDF (106/191 Pages) Motorola, Inc – Integrated EC000 Processor

Table 5-4. DRAM Bank Match Bits
A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17
0000 x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0001 •
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0010 •
•
x
x
x
x
x
x
x
x
x
x
x
x
x
0011 •
•
•
x
x
x
x
x
x
x
x
x
x
x
x
0100 •
•
•
•
x
x
x
x
x
x
x
x
x
x
x
0101 •
•
•
•
•
x
x
x
x
x
x
x
x
x
x
0110 •
•
•
•
•
•
x
x
x
x
x
x
x
x
x
0111 •
•
•
•
•
•
•
x
x
x
x
x
x
x
x
1000 •
•
•
•
•
•
•
•
x
x
x
x
x
x
x
1001 •
•
•
•
•
•
•
•
•
x
x
x
x
x
x
1010 •
•
•
•
•
•
•
•
•
•
x
x
x
x
x
1011 •
•
•
•
•
•
•
•
•
•
•
x
x
x
x
1100 •
•
•
•
•
•
•
•
•
•
•
•
x
x
x
1101 •
•
•
•
•
•
•
•
•
•
•
•
•
x
x
1110 •
•
•
•
•
•
•
•
•
•
•
•
•
•
x
1111 •
•
•
•
•
•
•
•
•
•
•
•
•
•
•
x = Address bit is a don’t care, DRA bit must be 0 to allow match.
• = Address bit must match DRA bit for DRAM bank to occur.
DRSZ—DRAM Size
DRAM address multiplexer provides (8 + DRSZ2–0) CAS address bits.
NOTE
Both DRAM banks must be the same size and speed. The
DRAM logic uses the DRSZ and DRDT values programmed in
the bank 0 configuration register only. These bits in the bank 1
configuration register are ignored.
DRDT—DRAM Automatic DTACK Response
0 = Automatic DTACK, 0 wait states
1 = Automatic DTACK, 1 wait state
NOTE
The write portion of a TAS is always 0-wait, regardless of the
state of DRDT.
5-16
MC68306 USER'S MANUAL
MOTOROLA