MC68306FC16 Datasheet, PDF (61/191 Pages) Motorola, Inc – Integrated EC000 Processor

The possible bus cycle terminations can be summarized as follows (case numbers refer to
Table 3-1).
Normal Termination: DTACK is asserted. BERR and HALT remain negated (case 1).
Halt Termination:
HALT is asserted coincident with or preceding DTACK, and
BERR remains negated (case 2).
Bus Error Termination: BERR is asserted in lieu of, coincident with, or preceding
DTACK (case 3).
Retry Termination:
HALT and BERR asserted in lieu of, coincident with, or before
DTACK (case 5).
Table 3-1 shows the details of the resulting bus cycle terminations for various
combinations of signal sequences.
Table 3-1. DTACK, BERR , and HALT Assertion Results
LEGEND:
Case
No.
1
2
3
4
5
6
Control Asserted on Rising
Signal
Edge of State
EC000 Core Results
N
N+2
DTACK
A
BERR
NA
HALT
NA
S
Normal cycle terminate and continue.
NA
X
DTACK
A
BERR
NA
HALT
A/S
S
Normal cycle terminate and halt. Continue
NA when HALT negated.
S
DTACK
X
BERR
A
HALT
NA
X
Terminate and take bus error trap.
S
NA
DTACK
A
BERR
NA
HALT
NA
S
Normal cycle terminate and continue.
A
NA
DTACK
X
BERR
A
HALT
A/S
X
Terminate and retry when HALT removed.
S
S
DTACK
A
BERR
NA
HALT
NA
S
Normal cycle terminate and continue.
A
A
N—
A—
NA —
X—
S—
The number of the current even bus state (e.g., S4, S6, etc.)
Signal asserted in this bus state
Signal not asserted in this bus state
Don't care
Signal asserted in preceding bus state and remains asserted in this state
NOTE: All operations are subject to relevant setup and hold times.
MOTOROLA
MC68306 USER'S MANUAL
3-29