MC68306FC16 Datasheet, PDF (126/191 Pages) Motorola, Inc – Integrated EC000 Processor

shown in Figure 6-9. The mode, status, command, and clock-select registers are
duplicated for each channel to provide independent operation and control.
NOTE
All serial module registers are only accessible as bytes. The
contents of the mode registers (DUMR1 and DUMR2), clock-
select register (DUCSR), and the auxiliary control register
(DUACR) bit 7 should only be changed after the
receiver/transmitter is issued a software RESET command—
i.e., channel operation must be disabled. Care should also be
taken if the register contents are changed during
receiver/transmitter operations, as undesirable results may be
produced.
In the registers discussed in the following pages, the numbers above the register
description represent the bit position in the register. The register description contains the
mnemonic for the bit. The values shown below the register description are the values of
those register bits after a hardware reset. A value of U indicates that the bit value is
unaffected by reset. The read/write status is shown in the last line.
Address
Register Read (R/W = 1)
Register Write (R/W = 0)
FFFFF7E1
MODE REGISTER A (DUMR1A, DUMR2A)
MODE REGISTER A (DUMR1A, DUMR2A)
FFFFF7E3
FFFFF7E5
STATUS REGISTER A (DUSRA)
DO NOT ACCESS1
CLOCK-SELECT REGISTER A (DUCSRA)
COMMAND REGISTER A (DUCRA)
FFFFF7E7
FFFFF7E9
RECEIVER BUFFER A (DURBA)
INPUT PORT CHANGE REGISTER (DUIPCR)
TRANSMITTER BUFFER A (DUTBA)
AUXILIARY CONTROL REGISTER (DUACR)
FFFFF7EB
FFFFF7ED
INTERRUPT STATUS REGISTER (DUISR)
COUNTER MODE:CURRENT MSB OF COUNTER
INTERRUPT MASK REGISTER (DUIMR)
COUNTER/TIMER UPPER REGISTER
FFFFF7EF
FFFFF7F1
COUNTER MODE:CURRENT LSB OF COUNTER
MODE REGISTER B (DUMR1B, DUMR2B)
COUNTER/TIMER LOWER REGISTER
MODE REGISTER B (DUMR1B, DUMR2B)
FFFFF7F3
FFFFF7F5
STATUS REGISTER B (DUSRB)
DO NOT ACCESS1
CLOCK-SELECT REGISTER B (DUCSRB)
COMMAND REGISTER B (DUCRB)
FFFFF7F7
FFFFF7F9
RECEIVER BUFFER B (DURBB)
INTERRUPT VECTOR REGISTER (DUIVR)
TRANSMITTER BUFFER B (DUTBB)
INTERRUPT VECTOR REGISTER (DUIVR)
FFFFF7FB
FFFFF7FD
FFFFF7FF
INPUT PORT REGISTER (DUIP)
START COUNTER COMMAND2
STOP COUNTER COMMAND2
OUTPUT PORT CONFIGURATION REGISTER
(DUOPCR)
OUTPUT PORT (DUOP) ² BIT SET
OUTPUT PORT (DUOP) ² BIT RESET
NOTES:
1. This address is used for factory testing and should not be read. Reading this location wiill result in undesired effects and
possible incorrect transmission or reception of characters. Register contents may also be changed.
2. Address-triggered commands
Figure 6-9. Serial Module Programming Model
6.4.1.1 MODE REGISTER 1 (DUMR1). DUMR1 controls some of the serial module
configuration. This register can be read or written at any time. It is accessed when the
6-18
MC68306 USER'S MANUAL
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