MC68306FC16 Datasheet, PDF (58/191 Pages) Motorola, Inc – Integrated EC000 Processor

S0 S2 S4 S6 S8
CLK
FC2-FC0
A23–A1
AS
LDS/UDS
R/W
DTACK
D15–D0
BERR
HALT
READ
≥1 CLOCK PERIOD
HALT
S0 S2 S4 S6
RETRY
Figure 3-25. Retry Bus Cycle Timing Diagram
The processor terminates the bus cycle, and remains in this state until HALT is negated.
Then the processor retries the preceding cycle using the same function codes, address,
and data (for a write operation). BERR should be negated at least one clock cycle before
HALT is negated.
NOTE
To guarantee that the entire read-modify-write cycle runs
correctly and that the write portion of the operation is
performed without negating the address strobe, the processor
does not retry a read-modify-write cycle. When BERR occurs
during a read-modify-write operation, a bus error operation is
performed whether or not HALT is asserted.
3.4.3 Halt Operation
HALT performs a halt/run/single-step operation. When HALT is asserted by an external
device, the processor halts and remains halted as long as the signal remains asserted, as
shown in Figure 3-26.
While the processor is halted, bus arbitration is performed as usual. Should a bus error
occur while HALT is asserted, the processor performs the retry operation previously
described.
NOTE
If a RESET instruction is executed while HALT is asserted, the
CPU will be reset.
3-26
MC68306 USER'S MANUAL
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