MC68306FC16 Datasheet, PDF (123/191 Pages) Motorola, Inc – Integrated EC000 Processor

MASTER STATION
TxD
A/D
ADDR
1
1
A/D
C0 0
A/D
ADDR
21
TRANSMITTER
ENABLED
TxRDY
(SR2)
CS
W
MR1(4:3) = 11
MR1(2) = 1
W
WW
ADDR1 MR1(2) = 0
PERIPHERAL
STATION
RxD
A/D
A/D
0
ADDR
1
1
MR1(2) = 1
WW
ADDR2
A/D
C0 0
A/D
A/D
ADDR
2
1
0
RECEIVER
ENABLED
CS
W
MR1(4–3) = 11
W
ENABLE
R
RR
ADDR STATUS DATA
C0
Figure 6-8. Multidrop Mode Timing Diagram
RR
STATUS DATA
ADDR
A transmitted character from the master station consists of a start bit, a programmed
number of data bits, an address/data (A/D) bit flag, and a programmed number of stop
bits. The A/D bit identifies the type of character being transmitted to the slave station. The
character is interpreted as an address character if the A/D bit is set or as a data character
if the A/D bit is cleared. The polarity of the A/D bit is selected by programming bit 2 of the
DUMR1. The DUMR1 should be programmed before enabling the transmitter and loading
the corresponding data bits into the transmit buffer.
In multidrop mode, the receiver continuously monitors the received data stream,
regardless of whether it is enabled or disabled. If the receiver is disabled, it sets the
RxRDY bit and loads the character into the receiver holding register FIFO stack provided
the received A/D bit is a one (address tag). The character is discarded if the received A/D
bit is a zero (data tag). If the receiver is enabled, all received characters are transferred to
the CPU via the receiver holding register stack during read operations.
MOTOROLA
MC68306 USER'S MANUAL
6-15