MC68306FC16 Datasheet, PDF (144/191 Pages) Motorola, Inc – Integrated EC000 Processor

6.4.1.19 OUTPUT PORT DATA REGISTER (DUOP). The bits in the DUOP register are
set by performing a bit set command (writing to $FFFFF7FD) and are cleared by
performing a bit reset command (writing to offset $FFFFF7FF).
Bit Set
DUOP
7
6
5
4
3
2
1
0
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
RESET:
0
0
0
0
0
0
0
0
Write Only
NOTE
The output port bits are inverted at the pins.
OP bits 7, 6, 5, 4, and 2 are not pinned out on the MC68306;
thus, changing these bits has no effect.
OP3, OP1, OP0 —Output Port Parallel Outputs
1 = A write cycle to the OP bit set command address sets all OP bits corresponding
to one bits on the data bus.
0 = These bits are not affected by writing a zero to this address.
Bit Reset
DUOP
7
6
5
4
3
2
1
0
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
RESET:
0
0
0
0
0
0
0
0
Write Only
OP3, OP1, OP0 —Output Port Parallel Outputs
1 = A write cycle to the OP bit reset command address clears all OP bits
corresponding to one bits on the data bus.
0 = These bits are not affected by writing a zero to this address.
6.4.1.20 Start Counter Command Register. A read at this address starts the
counter/timer. The read data has no meaning.
6.4.1.21 Stop Counter Command Register. A read at this address stops the counter and
clears the counter output (visible on OP3) if counter mode is selected. A read at this
address also clears DUISR CTR/TMR_RDY bit in counter or timer mode. The read data
has no meaning.
6-36
MC68306 USER'S MANUAL
MOTOROLA