MC68306FC16 Datasheet, PDF (104/191 Pages) Motorola, Inc – Integrated EC000 Processor

5.2.7.1 DRAM REFRESH REGISTER. The refresh timer is a programmable period
counter that generates a refresh request every 16 to 4096 EXTAL periods, programmable
in 16 EXTAL period increments.
FFFFFFFC
15
14
13
12
11
10
9
8
RR7 RR6 RR5 RR4 RR3 RR2 RR1 RR0
RESET
:
U
U
U
U
U
U
U
U
SUPERVISOR ONLY
RR7–0—Refresh Rate Period
The value set in this field supplies the refresh rate for the DRAM controller. The refresh
rate can be calculated from the equation:
Period = (16 × (register value +1)) × EXTAL
Where:
EXTAL is the crystal period in nanoseconds and period is in nanoseconds.
5.2.7.2 DRAM BANK CONFIGURATION REGISTER (HIGH HALF). The DRAM
configuration registers are not affected by any reset, and must be explicitly programmed.
This applies to both banks, whether used or not. Unused banks must be disabled to
prevent interference with other address decodes.
FFFFFFE4/5 (DR1), FFFFFFE0/1 (DR0)
15
14
13
12
11
10
DRA31 DRA3 DRA2 DRA2 DRA2 DRA2
0
9
8
7
6
RESE
T:
U
U
U
U
U
U
9
DRA2
5
U
8
DRA2
4
U
7
DRA2
3
U
6
DRA2
2
U
5
DRA21
4
DRA20
3
DRA19
2
1
DRA18 DRA1
7
0
DRW
U
U
U
U
U
U
SUPERVISOR ONLY
DRA31–DRA17—DRAM Bank Address
This bit field selects the base address for DRAM bank.
DRW—DRAM Write
This bit determines whether write cycles are permitted to DRAM bank space. If read and
write cycles are both inhibited, the DRAM bank is inhibited.
0 = Write cycles are inhibited to DRAM bank space
1 = Write cycles are permitted to DRAM bank space
NOTE
Never perform a TAS instruction to DRAM if the DRAM is
configured as write-only.
5-14
MC68306 USER'S MANUAL
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