MC68306FC16 Datasheet, PDF (172/191 Pages) Motorola, Inc – Integrated EC000 Processor

CLKOUT
S0 S1 S2 S3 S4 S5 S6 S7
FC2–FC0
A23–A1
AS
(NOTE 2)
LDS / UDS
R/W
(NOTE 2)
UW, LW
8
6
21
15
9
11A
17
18
11
20A
20
22
13
14
9
14A
9A
12
12A
DTACK
DATA OUT
BERR / BR
(NOTE 3)
HALT / RESET
ASYNCHRONOUS
INPUTS
(NOTE 1)
15A
47
55
26
7
23
48
47
47
47
32
32
56
47
28
53
25
30
NOTES:
1. Setup time (#47) for asynchronous inputs (HALT, RESET, BR, BGACK, DTACK, BERR, IRQx) guarantees
their recognition at the next falling edge of the clock.
2. Because of loading variations, R/W may be valid after AS even though both are initiated by the rising edge
of S2 (specification #20A).
3. BR need fall at this time only to ensure being recognized at the end of the bus cycle.
Figure 8-4. Write Cycle Timing Diagram
8-8
MC68306 USER'S MANUAL
MOTOROLA