MC68306FC16 Datasheet, PDF (62/191 Pages) Motorola, Inc – Integrated EC000 Processor

The negation of BERR and HALT under several conditions is shown in Table 3-2. (DTACK
is assumed to be negated normally in all cases; for reliable operation, both DTACK and
BERR should be negated when address strobe is negated).
EXAMPLE A:
A system uses a watchdog timer to terminate accesses to unused address space. The
timer asserts BERR after timeout (case 3).
EXAMPLE B:
A system uses error detection on random-access memory (RAM) contents. The system
designer may:
1. Delay DTACK until the data is verified. If data is invalid, return BERR and HALT
simultaneously to retry the error cycle (case 5).
2. Delay DTACK until the data is verified. If data is invalid, return BERR at the same
time as DTACK (case 3).
Table 3-2. BERR and HALT Negation Results
Conditions of
Termination in
Table 4-4
Control Signal
Bus Error
BERR
HALT
Rerun
BERR
HALT
Rerun
BERR
HALT
Normal
BERR
HALT
Normal
BERR
HALT
• = Signal is negated in this bus state.
Negated on Rising
Edge of State
N
N+2
Results—Next Cycle
•
or
• Takes bus error trap.
•
or
•
•
or
• Illegal sequence; usually traps to vector number 0.
•
•
Reruns the bus cycle.
•
•
May lengthen next cycle.
•
or
•
• If next cycle is started, it will be terminated as a bus
•
or none error.
3.7 ASYNCHRONOUS OPERATION
To achieve clock frequency independence at a system level, the bus can be operated in
an asynchronous manner. Asynchronous bus operation uses the bus handshake signals
to control the transfer of data. The handshake signals are AS, UDS, LDS , DTACK, BERR ,
and HALT. AS indicates the start of the bus cycle, and UDS and LDS signal valid data for
a write cycle. After placing the requested data on the data bus (read cycle) or latching the
data (write cycle), the slave device (memory or peripheral) asserts DTACK to terminate
the bus cycle. If no device responds or if the access is invalid, external control logic
asserts BERR , or BERR and HALT, to abort or retry the cycle. Figure 3-28 shows the use
of the bus handshake signals in a fully asynchronous read cycle. Figure 3-29 shows a fully
asynchronous write cycle.
3-30
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