MC68306FC16 Datasheet, PDF (140/191 Pages) Motorola, Inc – Integrated EC000 Processor

DBB—Delta Break B
1 = The channel B receiver has detected the beginning or end of a received break.
0 = No new break-change condition to report. Refer to 6.4.1.5 Command Register
(DUCR) for more information on the reset break-change interrupt command.
RxRDYB—Channel B Receiver Ready or FIFO Full
The function of this bit is programmed by DUMR1B bit 6. It is a duplicate of either the
FFULL or RxRDY bit of DUSRB.
TxRDYB—Channel B Transmitter Ready
This bit is the duplication of the TxRDY bit in DUSRB.
1 = The transmitter holding register is empty and ready to be loaded with a character.
0 = The transmitter holding register was loaded by the CPU, or the transmitter is
disabled. Characters loaded into the transmitter holding register when TxRDYx=0
are not transmitted.
CTR/TMR_RDY—Counter/Timer Ready
1 = Counter/timer ready.
0 = Counter/timer not ready.
DBA—Delta Break A. See DBB.
RxRDYA—Channel A Receiver Ready or FIFO Full. See RxRDYB.
The function of this bit is programmed by DUMR1A bit 6.
TxRDYA—Channel A Transmitter Ready. See TxRDYB.
This bit is the duplication of the TxRDY bit in DUSRA.
6.4.1.11 INTERRUPT MASK REGISTER (DUIMR). The DUIMR selects the corresponding
bits in the DUISR that cause an interrupt output (IRQ ). If one of the bits in the DUISR is
set and the corresponding bit in the DUIMR is also set, the IRQ output is asserted. If the
corresponding bit in the DUIMR is zero, the state of the bit in the DUISR has no effect on
the IRQ output. The DUIMR does not mask the reading of the DUISR.
DUIMR
7
6
5
4
3
2
1
0
COS
DBB
FFULLB TxRDYB CTR/TM
R
_RDY
DBA
FFULLA TxRDYA
RESET:
0
0
0
0
0
0
0
0
Write Only
COS—Change-of-State
1 = Enable interrupt
0 = Disable interrupt
6-32
MC68306 USER'S MANUAL
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