MC68306FC16 Datasheet, PDF (90/191 Pages) Motorola, Inc – Integrated EC000 Processor

Group
0
1
2
Table 4-6. Exception Grouping and Priority
Exception
Processing
Reset, Address Exception processing begins within two clock cycles.
Error, and Bus
Error
Trace, Interrupt, Exception processing begins before the next instruction.
Illegal, and
Privilege
TRAP, TRAPV, Exception processing is started by normal instruction execution.
CHK, and DIV
The priority relationship between two exceptions determines which is taken, or taken first,
if the conditions for both arise simultaneously. Therefore, if a bus error occurs during a
TRAP instruction, the bus error takes precedence, and the TRAP instruction processing is
aborted. In another example, if an interrupt request occurs during the execution of an
instruction while the T-bit in the status register (SR) is asserted, the trace exception has
priority and is processed first. Before instruction execution resumes, however, the interrupt
exception is also processed, and instruction processing finally commences in the interrupt
handler routine. As a general rule, the lower the priority of an exception, the sooner the
handler routine for that exception executes. This rule does not apply to the reset
exception; its handler is executed first even though it has the highest priority, because the
reset operation clears all other exceptions.
4-22
MC68306 USER'S MANUAL
MOTOROLA