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MC68306FC16 Datasheet, PDF (41/191 Pages) Motorola, Inc – Integrated EC000 Processor | |||
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CLK
A31âA1
S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19
AS
UDS OR LDS
R/W
DTACK
D15âD8 OR
D7âD0
FC2âFC0
INDIVISIBLE CYCLE
Figure 3-9. Read-Modify-Write Cycle Timing Diagram
The descriptions of the read-modify-write cycle states are as follows:
STATE 0
The read cycle starts in S0. The processor places valid function codes on
FC2âFC0, a valid address on the address bus, and drives R/W high to
identify a read cycle.
STATE 1 During S1, no bus signals are altered.
STATE 2 On the rising edge of S2, the processor asserts AS and UDS /LDS.
STATE 3 During S3, no bus signals are altered.
STATE 4
During S4, the processor waits for a cycle termination signal (DTACK or
BERR ). If neither termination signal is asserted before the falling
edge at the end of S4, the processor inserts wait states (full clock cycles)
until either DTACK or BERR is asserted.
Case R1: DTACK only.
STATE 5 During S5, no bus signals are altered.
STATE 6 During S6, data from the device are driven onto the data bus.
STATE 7
On the falling edge of the clock entering S7, the processor accepts data from
the device and negates UDS /LDS . The device negates DTACK at this
time.
STATES
8â11
The bus signals are unaltered during S8âS11, during which the arithmetic
logic unit makes appropriate modifications to the data.
MOTOROLA
MC68306 USER'S MANUAL
3-9
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