MC68306FC16 Datasheet, PDF (76/191 Pages) Motorola, Inc – Integrated EC000 Processor

Opcode
ABCD
ADD
ADDA
ADDI
ADDQ
ADDX
AND
ANDI
ANDI to CCR
ANDI to SR
ASL, ASR
Bcc
BCHG
BCLR
BRA
BSET
BSR
BTST
CHK
CLR
CMP
CMPA
CMPI
Table 4-4. EC000 Core Instruction Set Summary
Operation
BCD Source + BCD Destination + X ˘ Destination
Source + Destination ˘ Destination
Source + Destination ˘ Destination
Immediate Data + Destination ˘ Destination
Immediate Data + Destination ˘ Destination
Source + Destination + X ˘ Destination
Source Λ Destination ˘ Destination
Immediate Data Λ Destination ˘ Destination
Source Λ CCR ˘ CCR
If supervisor state
then Source Λ SR ˘ SR
else TRAP
Destination Shifted by count ˘ Destination
If condition true
then PC + d _n ˘ PC
~(bit number of Destination) ˘ Z;
~(bit number of Destination) ˘ (bit number) of
Destination
~(bit number of Destination) ˘ Z;
0 ˘ bit number of Destination
PC + d _n ˘ PC
~(bit number of Destination) ˘ Z;
1 ˘ bit number of Destination
SP – 4 ˘ SP; PC ˘ (SP); PC + d _n ˘ PC
–(bit number of Destination) ˘ Z;
If Dn < 0 or Dn > Source
then TRAP
0 ˘ Destination
Destination – Source ˘ cc
Destination – Source
Destination – Immediate Data
Syntax
ABCD Dy,Dx
ABCD –(Ay),–(Ax)
ADD <ea>,Dn
ADD Dn,<ea>
ADDA <ea>,An
ADDI #<data>,<ea>
ADDQ #<data>,<ea>
ADDX Dy,Dx
ADDX –(Ay),–(Ax)
AND <ea>,Dn
AND Dn,<ea>
ANDI #<data>,<ea>
ANDI #<data>,CCR
ANDI #<data>,SR
ASd Dx,Dy1
ASd #<data>,Dy1
ASd <ea>1
Bcc <label>
BCHG Dn,<ea>
BCHG #<data>,<ea>
BCLR Dn,<ea>
BCLR #<data>,<ea>
BRA <label>
BSET Dn,<ea>
BSET #<data>,<ea>
BSR <label>
BTST Dn,<ea>
BTST #<data>,<ea>
CHK <ea>,Dn
CLR <ea>
CMP <ea>,Dn
CMPA <ea>,An
CMPI #<data>,<ea>
4-8
MC68306 USER'S MANUAL
MOTOROLA