MC68306FC16 Datasheet, PDF (154/191 Pages) Motorola, Inc – Integrated EC000 Processor

An overview of the MC68306 implementation of IEEE 1149.1 is shown in Figure 7-1. The
MC68306 implementation includes a 16-state controller, a 3-bit instruction register, and
four test registers (a 1-bit bypass register, a 124-bit boundary scan register, a 3-bit module
mode register, and a 32-bit ID register). This implementation includes a dedicated TAP
consisting of the following signals:
TRST —
TCK —
TMS —
TDI —
TDO —
active low JTAG logic reset (with pullup).
test clock input to synchronize the test logic (with pulldown).
test mode select input (with an internal pullup resistor) that is sampled on the
rising edge of TCK to sequence the TAP controller's state machine.
test data input (with an internal pullup resistor) that is sampled on the rising
edge of TCK.
three-state test data output that is actively driven in the shift-IR and shift-DR
controller states. TDO changes on the falling edge of TCK.
2
0
MODE
31
0
ID
TEST DATA REGISTERS
M
123
0
U ID = 2040101D
X
BOUNDARY SCAN REGISTER
(124 BITS)
TDI
BYPASS
TRST
TMS
TCK
TAP
CTLR
DECODER
2
0
3-BIT INSTRUCTION REGISTER
M
U
X
TDO
Figure 7-1. Test Access Port Block Diagram
7-2
MC68306 USER'S MANUAL
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