MC68HC908AZ60 Datasheet, PDF (62/480 Pages) Motorola, Inc – HCMOS Microcontroller Unit

FLASH-2 Memory
FLASH Block Protection
NOTE:
In performing a program or erase operation the FLASH Block Protect
Register must be read after setting the PGM or ERASE bit and before
asserting the HVEN bit.
Due to the ability of the on-board charge pump to erase and program the
FLASH memory in the target application, provision is made for protecting
blocks of memory from unintentional erase or program operations due to
system malfunction. This protection is done by reserving a location in the
memory for block protect information and requiring that this location be
read before setting the HVEN bit. When the block protect register is
read, its contents are latched by the FLASH control logic. If the address
range for an erase or program operation includes a protected block, the
PGM or ERASE bit is cleared which prevents the HVEN bit in the FLASH
control register from being set so that no high voltage is allowed in the
array.
When the block protect register is erased (all 0s), the entire memory is
accessible for program and erase. When bits within the register are
programmed, they lock blocks of memory address ranges as shown in
FLASH Block Protect Register on page 60. The block protect register
itself can be erased or programmed only with an external voltage V_HI
present on the IRQ pin. The presence of V_HI on the IRQ pin also allows
entry in to monitor mode out of reset. Therefore, the ability to change the
block protect register is voltage dependent and can occur in either user
or monitor modes.
FLASH Block Protect Register
The block protect register for FLASH-2 is physically implemented as a
byte within the FLASH-1 memory. Please refer to the FLASH-1 memory
section, FLASH-2 Block Protect Register on page 48 for definition of this
register. Each bit, when programmed, protects a range of addresses in
the FLASH-2 array.
MC68HC908AZ60 — Rev 2.0
60
FLASH-2 Memory
10-flash-2
MOTOROLA