MC68HC908AZ60 Datasheet, PDF (43/480 Pages) Motorola, Inc – HCMOS Microcontroller Unit

FLASH-1 Memory
FLASH Charge Pump Frequency Control
PGM — Program Control Bit
This read/write bit configures the memory for program operation.
PGM is interlocked with the ERASE bit such that both bits cannot be
set at the same time.
1 = Program operation selected
0 = Program operation unselected
FLASH Charge Pump Frequency Control
The internal charge pump, required for program, margin read, and erase
operations, is designed to operate most efficiently with a 2MHz clock.
The charge pump clock is derived from the bus clock. Table 1 shows
how the FDIV bits are used to select a charge pump frequency based on
the bus clock frequency. Program, margin read and erase operations
cannot be performed if the bus clock frequency is below 2 MHz.
FDIV1
0
0
1
1
Table 1. Charge Pump Clock Frequency
FDIV0
0
1
0
1
Pump Clock Frequency
Bus Frequency ÷ 1
Bus Frequency ÷ 2
Bus Frequency ÷ 2
Bus Frequency ÷ 4
Bus Clock Frequency
2 MHz ± 10%
4 MHz ± 10%
4 MHz ± 10%
8 MHz ± 10%
NOTE: FDIV0 and FDIV1 must be set to the same value in both flash arrays.
FLASH Erase Operation
Memory Characteristics on page 445 has a detailed description of the
times used in this algorithm. Use the following procedure to erase a
block of FLASH memory:
1. Set the ERASE bit, the BLK0, BLK1, FDIV0, and FDIV1 bits in the
FLASH-1 control register. See Table 2 for block sizes. See Table
1 for FDIV settings.
7-flash-1
MOTOROLA
FLASH-1 Memory
MC68HC908AZ60 — Rev 2.0
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