MC68HC908AZ60 Datasheet, PDF (180/480 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Monitor ROM (MON)
V_DD
4096 + 32 CGMXCLK CYCLES
RST
24 CGMXCLK CYCLES
PA7
256 CGMXCLK CYCLES (ONE BIT TIME)
FROM HOST
PA0
1
4
1
1
2
4
1
FROM MCU
NOTE: 1 = Echo delay (2 bit times)
2 = Data return delay (2 bit times)
4 = Wait 1 bit time before sending next byte.
Figure 6. Monitor Mode Entry Timing
If the received bytes match those at locations $FFF6–$FFFD, the host
bypasses the security feature and can read all FLASH locations and
execute code from FLASH. Security remains bypassed until a power-on
reset occurs. After the host bypasses security, any reset other than a
power-on reset requires the host to send another eight bytes. If the reset
was not a power-on reset, the security remains bypassed regardless of
the data that the host sends.
If the received bytes do not match the data at locations $FFF6–$FFFD,
the host fails to bypass the security feature. The MCU remains in monitor
mode, but reading FLASH locations returns undefined data, and trying
to execute code from FLASH causes an illegal address reset. After the
host fails to bypass security, any reset other than a power-on reset
causes an endless loop of illegal address resets.
After receiving the eight security bytes from the host, the MCU transmits
a break character signalling that it is ready to receive a command.
NOTE: The MCU does not transmit a break character until after the host sends
the eight security bytes.
MC68HC908AZ60 — Rev 2.0
178
Monitor ROM (MON)
12-mon
MOTOROLA